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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Hao-Tien Lian | en |
dc.contributor.author | 連浩天 | zh_TW |
dc.date.accessioned | 2023-03-19T21:06:45Z | - |
dc.date.copyright | 2022-09-23 | |
dc.date.issued | 2022 | |
dc.date.submitted | 2022-09-20 | |
dc.identifier.citation | [1]SNIA [Online]. Available:http://www.snia.org/sites/default/files/RonEmerick_PCI _Express_IO_Virtuakization.pdf [2]An Inverter-Based Analog Front-End for a 56-Gb/s PAM-4 Wireline Transceiver in 16-nm CMOS,” IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 1, NO. 12, DECEMBER 2018 [3]A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS,”Department of Electrical Engineering, Stanford University, CA USA [4]PAM4 Signaling for 56G Serial Link Applications – A Tutorial [Online]. Available: https://www.xilinx.com/publications/events/designcon/2016/slidespam4signalingfor56gserial-zhang-designcon.pdf [5]A CIRCUIT FOR ALL SEASONS, The Acvive Inductor,” IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2020 [6]B. Nauta, “A CMOS transconductance-C filter technique for very high frequencies,” IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 142–153, Feb. 1992. [7]P. J. Peng et al., “A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS,” IEEE Int.Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2017, pp. 110–111. [8]PCI-SIG [Online]. Available: http://ww.pcisig.com/ [9]VLSI Limitations from Drain-induced Barrier Lowering,” RONALD R. TROUTMAN, SENIOR MEMBER, IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 2, APRIL 1979 [10]Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating Charu Gupta , Student Member, IEEE, Anshul Gupta , Student Member, IEEE, Reinaldo A. Vega, Member, IEEE, Terence B. Hook, and Abhisek Dixit , Senior Member, IEEE IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 5, MAY 2020 [11]R. Betancourt-Zamora and T. Lee, “Low phase noise CMOS ring oscillator VCOs for frequency synthesis,” in Proc. IEEE Int. Workshop Design Mixed Mode Integr. Circuits, Jul. 1998, pp. 1–4. [12]A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs Iat-Fai Sun, Jun Yin , Member, IEEE, Pui-In Mak , Senior Member, IEEE, and Rui P. Martins , Fellow, IEEE [13]A 4-to-16GHz Inverter-based Injection-Locked Quadrature Clock Generator with Phase Interpolators for Multi-standard I/Os in 7nm FinFET,” Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang ISSCC 2018 [14]A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator Guoying Wu, Student Member, IEEE, Deping Huang, Student Member, IEEE, Jingxiao Li, Ping Gui, Senior Member, IEEE, Tianwei Liu, Shita Guo, Rui Wang, Yanli Fan, Sudipto Chakraborty, and Mark Morgan IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 7, JULY 2016 [15]I.-F. Chen et al. “Loop latency reduction technique for all-digital clock and data recovery circuits,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 309–312. [16]Sonntag, L. Jeff, and Stonick, J.: ‘A digital clock and data recovery architecture for multi-gigabit/s binary links’, J. Solid-State Circuits, 2006, 41, pp. 1867–1875 [17]I.-F. Chen et al. “Loop latency reduction technique for all-digital clock and data recovery circuits,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 309–312. [18]A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET Alessandro Cevrero, Ilter Ozkaya, Pier Andrea Francese, Matthias Brandli, Christian Menolfi, Thomas Morf, Marcel Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl, IBM Research, Ruschlikon, Switzerland ,” ISSCC 2019 / SESSION 6 / ULTRA-HIGH-SPEED WIRELINE / 6.1 [19]A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET Alessandro Cevrero, Ilter Ozkaya1, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Brandli, Dan Kuchta, Lukas Kull, Jon Proesel, Marcel Kossel, Danny Luu, Benjamin Lee, Fuad Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl IBM Research, Rueschlikon, Switzerland, IBM Research, Yorktown Heights, NY, EPFL, Lausanne, SwitzerlandISSCC 2017 / SESSION 29 / OPTICAL- AND ELECTRICAL-LINK INNOVATIONS / 29.1 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83403 | - |
dc.description.abstract | 近年來由於物聯網、資料中心、人工智慧、機器學習等紛紛興起,面臨龐大的待處理資料,通訊系統對資料傳輸速率的要求呈現飛躍性的成長,包含SATA、PCIe、USB、乙太網路等,這種情況造就各種規格下的有線傳輸都必須縮短其世代更新的週期,以因應不斷推陳出新的各種應用。 作為個人電腦、伺服器及儲存裝置基礎I/O介面的PCIe,幾乎所有周邊裝置或其他I/O介面,都是透過PCIe來與運算核心連結。回顧PCIe協定的發展歷史,從PCIe1.0(2.5GT/s,2003)到PCIe3.0(8GT/s,2010)期間約是三至四年進行一次世代更新,更新至PCIe4.0(16GT/s,2017)卻花了七年的時間,我認為這是因為當時對於算力及資料傳輸速率的需求還沒有那麼緊湊。催生PCIe4.0推出的時間點恰巧是人工智慧、機器學習、邊緣運算等需要強力算力與資料傳輸速率的應用流行起來的時間點,而後僅花了兩年的時間PCIe5.0(32GT/s)便推出以支援這些新的應用。 作為各種規格的高速有線傳輸背後的核心技術SerDes,接收器在其中更是尤為重要的一塊。本論文所提出之32Gb/s不歸零碼接收器便是基於PCI-SIG所制定之PCIe5.0規格下所提出的設計,其中包含了基於反向器設計之連續時間等化器、基於反向器設計之可編程增益放大器、八個抽頭其中包含四個固定與四個可調整之決斷反饋等化器、一個抽頭的前饋式等化器、基於相位內插器之數位時脈資料回復電路及鎖相迴路,使用台積電12奈米工藝技術製造。PCIe5.0推出的三年後PCIe6.0(64GT/s)也在2022年推出,面臨如此高速的資料傳輸速率傳統的不歸零碼資料型式通道損耗過大,因此在PCIe6.0的世代將會全面啟用四階脈衝振幅調變的資料型式。本論文亦提出了一個以台積電40奈米工藝技術製造之80Gb/s四階脈衝振幅調變接收器,其中包含連續時間等化器、一個抽頭的前饋式等化器及一個抽頭的預測決斷反饋等化器。 | zh_TW |
dc.description.abstract | In recent years, due to the rise of the Internet of Things, data centers, artificial intelligence, machine learning, etc., facing the massive amount of data to be processed, the data transmission rate requirements of communication systems have shown rapid growth, including SATA, PCIe, USB, and Ethernet networks, etc. The wireline communication under various specifications must shorten the cycle of its generational update in order to cope with the continuous introduction of new applications. PCIe is the primary I/O interface of personal computers, servers, and storage devices. Almost all peripheral devices or other I/O interfaces are connected to the computing core through PCIe. Looking back at the development history of the PCIe protocol, from PCIe 1.0 (2.5GT/s, 2003) to PCIe 3.0 (8GT/s, 2010), a generational update was performed every three to four years, and it was updated to PCIe 4.0 (16GT/s, 2017), but it took seven years. I think this is because the demand for computing power and the data transfer rate were not so tight at that time. The launch of PCIe 4.0 coincides with the time when applications that require powerful computing power, such as artificial intelligence, machine learning, and edge computing, have become popular. Then it took only two years for PCIe 5.0 (32GT/s) to be launched to support these new applications. As the core technology behind the high-speed wireline communication of various specifications, SerDes, the receiver, is a critical piece. The 32Gb/s non-return-to-zero code receiver proposed in this paper is based on the design proposed under the PCIe5.0 specification formulated by PCI-SIG, which includes a continuous-time equalizer based on an inverter design, an inverter-based programmable gain amplifier, eight taps including four fixed and four adjustable decision feedback equalizers, one tap feedforward equalizer, digital clock data recovery based on phase interpolator and PLL.The circuits are fabricated in TSMC's 12nm process technology. Three years after PCIe5.0 was launched, PCIe6.0 (64GT/s) will also be launched in 2022. In the face of such a high-speed data transmission rate, the traditional NRZ data transmission type channel loss is too significant so that the PCIe6.0 generation will be Fully enabled fourth order pulse amplitude modulation data type. This paper also proposes an 80Gb/s PAM4 receiver fabricated on TSMC's 40nm process technology, which includes a continuous-time equalizer, a one-tap feed-forward equalizer, and a one-tap look-ahead decision Feedback equalizer. | en |
dc.description.provenance | Made available in DSpace on 2023-03-19T21:06:45Z (GMT). No. of bitstreams: 1 U0001-0409202213541200.pdf: 6435285 bytes, checksum: 4bdbfe46e33fa50898928d11ec8d4060 (MD5) Previous issue date: 2022 | en |
dc.description.tableofcontents | 口試委員會審定書 # 中文摘要 i ABSTRACT iii CONTENTS vi LIST OF FIGURES viii LIST OF TABLES xv Chapter1 Introduction 1 1.1 Motivation 1 1.2 Dissertation Organization 5 Chapter 2 Introduction of PCI Express 6 Chapter 3 A 32G-b/s NRZ Receiver circuit 11 3.1 Architecture and Building Blocks 11 3.2 Inverter-based Analog Front-end Circuit 13 3.2.1 Continuous Time Linear Equalizer 13 3.2.2 Inverter-based Continuous Time Linear Equalizer 24 3.2.3 Programmable Gain Amplifier 50 3.3 Phase Locked Loop Circuit 52 3.3.1 Phase Frequency Detector 52 3.3.2 Charge Pump 57 3.3.3 Voltage Controlled Oscillator 61 3.3.4 Phase-Locked Loop 71 3.4 Clock and Data Recovery Circuit 77 3.4.1 Phase Detector 77 3.4.2 Majority Voter 79 3.4.3 Phase Interpolator 80 3.4.4 All Digital CDR Behavior 84 Chapter 4 A 112G-b/s PAM4 Receiver Circuit 92 4.1 Architecture and Building Blocks 92 4.2 Feedforward Equalizer 95 4.3 Decision Feedback Equalizer 102 Chapter 5 Measurement 106 5.1 Measurement Setup 106 5.2 Measurement Results 109 Chapter 6 Conclusions 113 REFERENCE 115 | |
dc.language.iso | en | |
dc.title | 應用於32-Gb/s不歸零碼接收器與112-Gb/s四階脈衝振幅調變接收器之電路設計 | zh_TW |
dc.title | Circuit Design for 32-Gb/s NRZ Receiver and 112-Gb/s PAM4 Receiver | en |
dc.type | Thesis | |
dc.date.schoolyear | 110-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 彭朋瑞(Pen-Jui Peng) | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 基於反向器設計之連續時間等化器,基於反向器設計之可編程增益放大器,決斷反饋等化器,前饋式等化器,相位內插器,數位時脈資料回復電路,鎖相迴路, | zh_TW |
dc.subject.keyword | Inverter-based continuous time linear equalizer,Inverter-based programmable gain amplifier,Decision feedback equalizer,Feedforward equalizer,Phase interpolator,Digital CDR,Phase locked loop, | en |
dc.relation.page | 117 | |
dc.identifier.doi | 10.6342/NTU202203128 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2022-09-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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