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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | zh_TW |
dc.contributor.advisor | Chien-Mo Li | en |
dc.contributor.author | 陳淳 | zh_TW |
dc.contributor.author | Chun Chen | en |
dc.date.accessioned | 2023-02-01T17:08:51Z | - |
dc.date.available | 2023-11-09 | - |
dc.date.copyright | 2023-02-01 | - |
dc.date.issued | 2022 | - |
dc.date.submitted | 2023-01-12 | - |
dc.identifier.citation | [1] D. Appello, H. Chen, M. Sauer, I. Polian, P. Bernardi, and M. S. Reorda, “Systemlevel test: State of the art and challenges,” in 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021.
[2] S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,” Ieee Micro, vol. 25, no. 6, pp. 10–16, 2005. [3] R. Cantoro, M. Huch, T. Kilian, R. Martone, U. Schlichtmann, and G. Squillero,“Machine learning based performance prediction of microcontrollers using speed monitors,” in 2020 IEEE International Test Conference (ITC), 2020. [4] J. T.-Y. Chang and E. J. McCluskey, “Detecting delay flaws by very-low-voltage testing,” in Proceedings International Test Conference 1996. Test and Design Validity. IEEE Computer Society, 1996. [5] H. H. Chen, S.-H. Kuo, J. Tung, and M. C.-T. Chao, “Statistical techniques for preicting system-level failure using stress-test data,” in 2015 IEEE 33rd VLSI Test Symposium (VTS), 2015. [6] J. Chen, L.-C. Wang, P.-H. Chang, J. Zeng, S. Yu, and M. Mateja, “Data learning techniques and methodology for fmax prediction,” in 2009 International Test Conference, 2009. [7] T. Chen and C. Guestrin, “Xgboost: A scalable tree boosting system,” in Proceedings of the 22nd acm sigkdd international conference on knowledge discovery and data mining, 2016. [8] D. Freedman, R. Pisani, and R. Purves, “Statistics (international student edition),” Pisani, R. Purves, 4th edn. WW Norton & Company, New York, 2007. [9] S. Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, and X. Wen, “Logic fault diagnosis of hidden delay defects,” in 2020 IEEE International Test Conference (ITC), 2020. [10] Y.-T. Kuo, W.-C. Lin, C. Chen, C.-H. Hsieh, C.-M. Li, E. J.-W. Fang, and S. S.-Y. Hsueh, “Minimum operating voltage prediction in production test using accumulative learning,” in 2021 IEEE International Test Conference (ITC), 2021. [11] J. Lee, D. Walker, L. Milor, Y. Peng, and G. Hill, “Ic performance prediction for test cost reduction,” in 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No. 99CH36314), 1999. [12] W.-C. Lin, C. Chen, C.-H. Hsieh, C.-M. Li, E. J.-W. Fang, and S. S.-Y. Hsueh, “Mlassisted vmin binning with multiple guard bands for low power consumption,” in 2022 IEEE International Test Conference (ITC), 2022. [13] S.-P. Mu, M. C.-T. Chao, S.-H. Chen, and Y.-M. Wang, “Statistical framework and built-in self-speed-binning system for speed binning using on-chip ring oscillators,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1675–1687, 2015. [14] F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion, O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg, J. Vanderplas, A. Passos, D. Cournapeau, M. Brucher, M. Perrot, and E. Duchesnay, “Scikit-learn: Machine learning in Python,” Journal of Machine Learning Research, vol. 12, pp. 2825–2830, 2011. [15] P. Sprent, Applied nonparametric statistical methods. Springer Science & Business Media, 2012. [16] M.-Y. Su, W.-C. Lin, Y.-T. Kuo, C.-M. Li, E. J.-W. Fang, and S. S.-Y. Hsueh, “Chip performance prediction using machine learning techniques,” in 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2021. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83262 | - |
dc.description.abstract | 我們運用非破壞性壓力測試提出了一個全新的晶片最小工作電壓預測流程,其能避免面積代價並且能減少測試時間。我們將測試 fail-log 經過加總處理成 MMC 數據。我們使用三種策略: CYSO、 PSSY 以及 PSSO 策略來產生 MMC,並且使用 MMC 來預測晶片最小工作電壓。除此之外,我們選出與最小工作電壓相關的重要測試圖樣來減少測試時間。我們使用斯皮爾曼等級相關係數來找出重要的 MMC 索引值,並且使用模擬退火法在可接受的時間之內找出重要的測試圖樣子集合。我們採用線性回歸與極限梯度提昇回歸模型來進行實驗。在先進的 7 奈米與 3 奈米晶片上的實驗結果顯示,使用 CYSO 策略搭配線性回歸模型來預測最小工作電壓可以僅有 4.48 至 8.66 毫伏特的均方根誤差。並且,根據實驗結果,我們的測試圖樣選擇流程可以減少 354 至 948 倍的測試圖樣。我們所提出的流程能夠有比 process monitor 方法還要小的均方根誤差,並且與傳統測試方法相比,有 50 至 62.5 倍的時間加速。 | zh_TW |
dc.description.abstract | We propose a novel minimum operating voltage (Vmin) prediction flow using nondestructive stress-test to avoid area overhead and reduce test time. We process stress-test fail-logs and generate summation values, which is called MMC. Three strategies: CYSO, PSCY and PSSO strategies are used to generate MMC. Then, we use MMC to predict Vmin. In addition, we select important test patterns that correlated to Vmin to reduce test time. We use Spearman Correlation to find important MMC-Indices. Also, we use simulated annealing to select important test pattern subsets in an acceptable time. Two regression models, linear regression and XGBoost regression, are adopted in our experiment. Experimental results on advanced 7nm and 3nm chip designs show that the average RMSE of our predict Vmin can be as low as 4.48 mV to 8.66mV by CYSO strategy with linear regression model. Moreover, our test pattern selection flow can have 354 to 948 times test pattern reduction. Our flow gives smaller RMSE than the process monitor flow, and is 50 to 62.5 times faster compared to the conventional testing flow. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-02-01T17:08:51Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2023-02-01T17:08:51Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 致謝 i
摘要 iii Abstract iv Contents v List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique 4 1.3 Contributions 5 1.4 Organization 6 Chapter 2 Background 7 2.1 Previous Work 7 2.2 Stress Test 10 2.3 Spearman Correlation 16 2.4 Machine Learning Regression Models 18 2.4.1 Linear Regression 19 2.4.2 XGBoost Regression 21 Chapter 3 Proposed Technique 24 3.1 Overall Flow 24 3.2 Stress-test Fail-logs and MMC 26 3.3 MMC-Index Selection 31 3.4 Test Pattern Selection and Re-generate MMC 33 3.5 Build a Vmin Prediction Model 37 Chapter 4 Experimental Results 38 4.1 Experimental Setup 38 4.2 Determine Kf and Kp 39 4.3 Prediction RMSE 40 4.4 Benefits of Test Pattern Selection and Reduction 43 4.5 Test Application Time Reduction 44 Chapter 5 Discussion 46 5.1 Under-prediction Issue 46 5.2 Diagnosis of Stress-test Fail-logs 47 Chapter 6 Conclusion 49 References 50 | - |
dc.language.iso | en | - |
dc.title | 使用非破壞性壓力測試預測晶片最小工作電壓 | zh_TW |
dc.title | Vmin Prediction Using Nondestructive Stress Test | en |
dc.title.alternative | Vmin Prediction Using Nondestructive Stress Test | - |
dc.type | Thesis | - |
dc.date.schoolyear | 111-1 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 吳安宇;方家偉;陳海力 | zh_TW |
dc.contributor.oralexamcommittee | An-Yeu Wu;Jia-Wei Fang;Harry-H Chen | en |
dc.subject.keyword | 晶片效能預測,非破壞性壓力測試, | zh_TW |
dc.subject.keyword | Chip performance prediction,Nondestructive stress test, | en |
dc.relation.page | 52 | - |
dc.identifier.doi | 10.6342/NTU202210116 | - |
dc.rights.note | 同意授權(限校園內公開) | - |
dc.date.accepted | 2023-01-13 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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