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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為 | zh_TW |
| dc.contributor.advisor | Chee Wee Liu | en |
| dc.contributor.author | 林宇軒 | zh_TW |
| dc.contributor.author | Yuxuan Lin | en |
| dc.date.accessioned | 2023-01-10T17:12:36Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-01-07 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2002-01-01 | - |
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Zhao et al., "Engineering Hf0.5Zr0.5O2 Ferroelectric/Anti- Ferroelectric Phases With Oxygen Vacancy and Interface Energy Achieving High Remanent Polarization and Dielectric Constants," in IEEE Electron Device Letters, vol. 43, no. 4, pp. 553-556, April 2022, doi: 10.1109/LED.2022.3149309. [15] Müller J, Böscke T S, Bräuhaus D, et al. Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications [J]. Applied Physics Letters, 2011, 99(11): 112901. [16] Sheng-Ting Fan, Yun-Wen Chen and C W Liu, "Strain effect on the stability in ferroelectric HfO2 simulated by first-principles calculations," J. Phys. D: Appl. Phys, 2020, doi: 10.1088/1361-6463/ab7fd4 [17] Zhuravlev, M. Y., Sabirianov, R. F., Jaswal, S. S. & Tsymbal, E. Y. Phys. Rev. Lett. 94, 246802 ,2005. [18] Mehta R, Silverman B D, Jacobs J T. Depolarization Fields in Thin Ferroelectric Films [J]. Journal of Applied Physics, 1973, 44(8): 3379-3385. [19] H. . -L. Chiang et al., "Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, pp. 361-362, doi: 10.1109/VLSITechnologyandCir46769.2022.9830462. [20] Yurchuk E, Müller J, Knebel S, et al. Impact of layer thickness on the ferroelectric behaviour of silicon doped hafnium oxide thin films [J]. Thin Solid Films, 2013, 533: 88-92. [21] Kohlstedt, H., Pertsev, N. A., Rodríguez Contreras, J. & Waser, R. Phys. Rev. B 72, 125341 ,2005. [22] Steven A et al., Transferred Electron Devices, 2011 [23] G. N. Derry and Zhang Ji-Zhong, "Work function of Pt(111) ", Phys. Rev. B 39, 1940 – Published 15 January 1989, doi: 10.1103/PhysRevB.39.1940 [24] A. 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Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices. Nat Commun 4, 1624 (2013). doi: 10.1038/ncomms2652 [35] Laturia, A., Van de Put, M.L. & Vandenberghe, W.G. Dielectric properties of hexagonal boron nitride and transition metal dichalcogenides: from monolayer to bulk. npj 2D Mater Appl 2, 6 (2018). https://doi.org/10.1038/s41699-018-0050-x [36] Mahvash, F., Eissa, S., Bordjiba, T. et al. Corrosion resistance of monolayer hexagonal boron nitride on copper. Sci Rep 7, 42139 (2017). doi:10.1038/srep42139 [37] Andrea Crovetto, Patrick Rebsdorf Whelan, Ruizhi Wang, Miriam Galbiati, Stephan Hofmann, and Luca Camilli, "Nondestructive Thickness Mapping of Wafer-Scale Hexagonal Boron Nitride Down to a Monolayer," ACS Appl. Mater. Interfaces 2018, 10, 30, 25804–25810, doi: 10.1021/acsami.8b08609 [38] Resta R, Vanderbilt D. Theory of polarization: a modern approach [J]. Physics of Ferroelectrics, 2007: 31-68. [39] Sawyer C B, Tower C H. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83186 | - |
| dc.description.abstract | 本篇論文是基於氧化鋯鉿(Hf0.5Zr0.5O2, HZO)鐵電穿隧接面(Ferroelectric Tunnel Junction, FTJ)記憶體的模擬和實驗。經過對物理性質的分析後，通過帕松方程式(Poisson equation)和WKB近似的模擬討論了不同性質的界面層(Interfacial layer，IL)對鐵電穿隧接面電流表現的影響，提出了一種提高鐵電穿隧接面性能的結構。根據所提出結構的實驗量測結果討論製程過程對殘餘極化量（remnant polarization，Pr）和電流開關比（on-off ratio）的影響。最後建立一個理論模型評估鐵電穿隧接面記憶體在交叉點記憶體陣列（cross-point memory array）中的應用。
鐵電材料有兩種穩定且相反的極化狀態，當外加偏壓超過反轉電壓（coercive voltage）的時候會改變材料極化狀態。氧化鋯鉿作為一種鐵電材料，由於與CMOS兼容並且可以進一步微縮所以受到越來越多的關注。基於氧化鋯鉿的鐵電穿隧接面記憶體可以在零偏壓的時候根據氧化鋯鉿的極化狀態表現出高阻態（high resistance state，HRS）和低阻態（low resistance state，LRS）特性，具有非揮發性記憶體（Non-volatile Memory, NVM）特性。相比起傳統鐵電穿隧接面的金屬-鐵電材料-金屬結構，金屬-電介質-鐵電材料-金屬結構因為具有更顯著的開關比和更大的開電流，成為了現在的研究熱點。由於鐵電穿隧接面作為優秀的新興記憶體（emerging memory），在交叉點記憶體陣列等多方面應用上是非常有潛力的候選者。 在第二章中介紹了鐵電穿隧接面的能階圖計算原理和材料參數對能階圖的影響。通過分析能階圖得到後續電流計算需要的關鍵參數。介紹了基於能階圖的穿隧電流計算模型。對比使用不同材料的鐵電穿隧接面的模擬結果，根據對比結果提出了一種能夠提升元件表現的鐵電穿隧接面結構。 在第三章中，根據理論模型提出的元件結構，結合成熟的MFM結構鐵電穿隧接面製程進行製程設計。選擇合適的量測方法對元件進行電性量測，對不同製程條件的樣品量測結果進行分析，討論了製程的改進方向。 第四章在基於單一元件的電流模擬之上，對鐵電穿隧接面記憶體在交叉點記憶體陣列上的應用進行了討論。根據交叉點記憶體陣列電路建立了一個簡易模型。這個模型可以根據單一元件的表現評估最壞情況下這種元件所組成的交叉點記憶體陣列規模。最後根據模擬結果提出最適合交叉點記憶體陣列的元件結構。 | zh_TW |
| dc.description.abstract | This dissertation is based on the simulation and experiment of Ferroelectric Tunnel Junction (FTJ) of Hf0.5Zr0.5O2 (HZO). After analyzing the physical properties, the effects of different properties of the interfacial layer (IL) on the current performance of the FTJ are discussed by the Poisson equation and WKB approximation simulations, and a structure to improve the performance of the FTJ is proposed. Based on the experimental measurements of the proposed structure, methods to improve the remnant polarization (Pr) and on-off ratio by process are discussed. Finally, a theoretical model is developed to evaluate the application of FTJ in cross-point memory array.
Ferroelectric materials have two stable and opposite polarization states, which are changed when the applied bias voltage (Vapp) exceeds the coercive voltage (Vc). HZO is a ferroelectric material that has received increasing attention because of its compatibility with CMOS and its ability to scale. HZO-based FTJ can exhibit high resistance state (HRS) and low resistance state (LRS) depending on the polarization state of HZO at zero bias voltage, having non-volatile memory (NVM) characteristics. Compared with the conventional Metal-Ferroelectric-Metal (MFM) structure FTJ, the Metal-Insulator-Ferroelectric-Metal (MIFM) structure FTJ has become a hot research topic due to its higher on-off ratio and on current. In addition to being an excellent emerging memory, FTJ is also a promising candidate for cross-point memory array. Chapter two introduce the principle of band diagram calculation and the influence of material parameters on the band diagram of FTJ. The key parameters required for the subsequent current calculation are obtained by analyzing the band diagram. The model for the calculation of the tunneling current based on the band diagram is presented. Based on the comparison of FTJ simulation results of different materials, an FTJ structure is proposed to improve the performance of components. In Chapter three, according to the proposed MIFM structure FTJ and the known MFM structure FTJ process, the process design is carried out based on the material characteristics of MIFM FTJ. The sample measurement results of different processes were analyzed and the direction of process improvement was discussed. Chapter four discusses the application of FTJ in cross-point memory array based on the current simulation in chapter two. An evaluation model is developed based on the cross-point memory array circuit. This model allows the evaluation of the worst-case cross-point memory array size of such FTJ based on the performance of a single FTJ. Finally, according to the comparison of simulation results, the most suitable FTJ structure for cross-point memory array is proposed. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-01-10T17:12:36Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-01-10T17:12:36Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 II
摘要 III ABSTRACT V CONTENT VII LIST OF FIGURES X LIST OF TABLES XII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Band Diagram and Current Model of FTJ 4 2.1 Introduction 4 2.1.1 FTJ and WKB Approximation 4 2.1.2 Band Diagram 4 2.2 Band Diagram Model 5 2.2.1 Simulation Parameter 5 2.2.2 Electrostatic Model 6 2.2.2.1 Electrostatic Model at Vapp =0 6 2.2.2.2 Electrostatic Model at Vapp≠0 8 2.2.2.3 Electrostatic Model for Different Electrodes 10 2.2.2.4 Model Formula Integration 11 2.3 Tunneling current model 11 2.3.1 Tunneling Mechanism and Critical Conditions 12 2.3.1.1 Tunneling Mechanism 12 2.3.1.2 Tunneling Distance and Effective Barrier 12 2.3.2 Tunneling Current Model 13 2.3.3 Asymmetric I-V Curves of Asymmetric Structures 14 2.3.4 Influence of Different Parameters 16 2.3.4.1 FE Layer Remnant Polarization（Pr） 16 2.3.4.1 FE Layer Thickness 16 2.3.4.2 IL Thickness 17 2.3.4.3 IL Electron Affinity 18 2.3.4.4 IL Permittivity（K value） 19 2.3.4.5 Summary 20 2.3.5 Ideally Structured Based on Simulation 21 2.4 Summary 22 Chapter 3 Fabrication and Electrical Analysis of FTJ 23 3.1 Introduction 23 3.2 Fabrication of FTJ 23 3.2.1 MFM Fabrication and Process Flow 23 3.2.2 MIFM Fabrication and Process Flow 24 3.3 Electrical Measurement of FTJ 25 3.3.1 IV Measurement 25 3.3.2 PV Measurement 26 3.3.3 CV Measurement 27 3.3.3.1 Measurement Methods for Different Conditions 27 3.3.3.2 Analysis of Measurement Results 28 3.4 Electrical Analysis of Different Structure FTJ 29 3.4.1 Electrical Difference of MIFM and MFM 29 3.4.2 Presumptions Based on Measurement Results 31 3.4.3 Process Modification Solutions 31 3.5 Summary 32 Chapter 4 Application of FTJ in Cross-point Memory Arrays 33 4.1 Introduction 33 4.2 Estimation Model of Array Size 33 4.2.1 Equivalent Circuit of 1×1 Array 33 4.2.2 Equivalent Circuit and Worst Case for 2×2 Array 34 4.2.3 Equivalent Circuit and Operability Evaluation for n×n Array 35 4.3 Influence of Different Parameters 37 4.3.1 IL Thickness 37 4.3.2 IL Electron Affinity 37 4.3.3 IL Permittivity（K value） 38 4.4 FTJ of Different ILs in Cross-point Memory Arrays 39 4.5 Summary 40 Chapter 5 Summary and Future Work 42 5.1 Summary 42 5.2 Future Work 43 Reference 44 | - |
| dc.language.iso | en | - |
| dc.subject | 非揮發性記憶體 | zh_TW |
| dc.subject | 交叉點記憶體陣列 | zh_TW |
| dc.subject | HfxZr1-xO2薄膜 | zh_TW |
| dc.subject | 鐵電材料 | zh_TW |
| dc.subject | 鐵電穿隧接面 | zh_TW |
| dc.subject | 穿隧電流 | zh_TW |
| dc.subject | Cross-point memory array | en |
| dc.subject | Non-volatile Memory | en |
| dc.subject | HZO | en |
| dc.subject | Ferroelectric Tunnel Junction (FTJ) | en |
| dc.subject | Ferroelectric | en |
| dc.subject | Tunneling Current | en |
| dc.title | 具有界面層的鐵電穿隧接面的模擬與電性 | zh_TW |
| dc.title | The Simulation and Electrical Characterization of Ferroelectric Tunnel Junctions with Interfacial Layers | en |
| dc.title.alternative | The Simulation and Electrical Characterization of Ferroelectric Tunnel Junctions with Interfacial Layers | - |
| dc.type | Thesis | - |
| dc.date.schoolyear | 110-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 廖洺漢;李敏鴻;林楚軒;林吉聰 | zh_TW |
| dc.contributor.oralexamcommittee | Ming Han Liao;Min-Hung Lee;Chu-Hsuan Lin;Jyi-Tsong Lin | en |
| dc.subject.keyword | 鐵電材料,鐵電穿隧接面,穿隧電流,非揮發性記憶體,HfxZr1-xO2薄膜,交叉點記憶體陣列, | zh_TW |
| dc.subject.keyword | Ferroelectric,Ferroelectric Tunnel Junction (FTJ),Tunneling Current,Non-volatile Memory,HZO,Cross-point memory array, | en |
| dc.relation.page | 48 | - |
| dc.identifier.doi | 10.6342/NTU202203547 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2022-09-27 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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