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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83127完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | zh_TW |
| dc.contributor.advisor | Hsin-Shu Chen | en |
| dc.contributor.author | 廖亦勛 | zh_TW |
| dc.contributor.author | Yi-Hsun Liao | en |
| dc.date.accessioned | 2023-01-09T06:29:25Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-01-06 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2022-11-15 | - |
| dc.identifier.citation | [ 1 ] G. -Y. Huang, S. -J. Chang, C. -C. Liu and Y. -Z. Lin, "A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications," in IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012.
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Chen, "An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration," 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018, pp. 253-256. [ 7 ] F. Chiang, et al., “All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter” 2019 [ 8 ] W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011. [ 9 ] Yuan Zhou, Benwei Xu and Yun Chiu, "A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration," 2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, pp. 1-2. [ 10 ] W. -H. Tseng, W. -L. Lee, C. -Y. Huang and P. -C. Chiu, "A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters," in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Oct. 2016. [ 11 ] D. -J. Chang, W. Kim, M. -J. Seo, H. -K. Hong and S. -T. Ryu, "Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 322-332, Feb. 2017. [ 12 ] C. C. Lee, C. -Y. Lu, R. Narayanaswamy and J. B. Rizk, "A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS," 2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, pp. C62-C63. [ 13 ] T. Miki et al., "A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, June 2015. [ 14 ] P. Harpe, E. Cantatore and A. van Roermund, "11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 194-195. [ 15 ] P. Harpe, E. Cantatore and A. van Roermund, "A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3011-3018, Dec. 2013. [ 16 ] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [ 17 ] T. Sepke, P. Holloway, C. G. Sodini and H. -S. Lee, "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009. [ 18 ] F. van der Goes et al., "A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2835-2845, Dec. 2014. [ 19 ] Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, "A low-noise self-calibrating dynamic comparator for high-speed ADCs," 2008 IEEE Asian Solid-State Circuits Conference, 2008, pp. 269-272. [ 20 ] S. Babayan-Mashhadi and R. Lotfi, "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014. [ 21 ] Y. Zhu, C. -H. Chan, S. -P. U and R. P. Martins, "An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1223-1234, May 2016. [ 22 ] B. -R. -S. Sung et al., "A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration," 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, pp. 281-284. [ 23 ] W. Li, F. Li, J. Liu, H. Li and Z. Wang, "A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator," 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, pp. 225-228. [ 24 ] Yoshioka M, Ishikawa K, Takayama T, Tsukamoto S. A 10-b 50-MS/s 820- μW SAR ADC With On-Chip Digital Calibration. IEEE Trans Biomed Circuits Syst. 2010 Dec;4(6):410-6. [ 25 ] M. Ding, P. Harpe, Y. -H. Liu, B. Busze, K. Philips and H. de Groot, "A 46 uW 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 423-432, Feb. 2017. [ 26 ] C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [ 27 ] S. -W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13um CMOS," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. [ 28 ] Y. -S. Hu, K. -Y. Lin and H. -S. Chen, "A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique," 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, pp. 149-152. [ 29 ] V. Hariprasath, et al., "Merged capacitor switching based SAR ADC with highest switching energy-efficiency," in Electronics Letters, vol. 46, no. 9, pp. 620-621, 29 April 2010. [ 30 ] F. Kuttner, "A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS," 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, pp. 176-177 vol.1. [ 31 ] C. -C. Liu et al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," 2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, pp. 386-387. [ 32 ] B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," in IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, April 2007. [ 33 ] R. Kapusta, J. Shen, S. Decker, H. Li, E. Ibaragi and H. Zhu, "A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3059-3066, Dec. 2013. [ 34 ] M. J. Kramer, E. Janssen, K. Doris and B. Murmann, "A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2891-2900, Dec. 2015. [ 35 ] M. Shim et al., "Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1077-1090, April 2017. [ 36 ] J. Zhong, Y. Zhu, C. -H. Chan, S. -W. Sin, S. -P. U. and R. P. Martins, "A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 7, pp. 1684-1695, July 2017. [ 37 ] S. -E. Hsieh and C. -C. Hsieh, "A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 240-242. [ 38 ] J. Shen et al., "A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1149-1160, April 2018. [ 39 ] Z. Ding, X. Zhou and Q. Li, "A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator," 2018 IEEE Symposium on VLSI Circuits, 2018, pp. 93-94. [ 40 ] H. Huang, L. Du and Y. Chiu, "A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer," in IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1551-1562, June 2017. [ 41 ] M. Hesener, T. Eicher, A. Hanneberg, D. Herbison, F. Kuttner and H. Wenske, "A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS," 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, pp. 248-600. [ 42 ] D. Johns and K. Martin, Analog Integrated Circuit Design, New York, USA: Wiley, 1997. [ 43 ] H. -Y. Tai, H. -W. Chen and H. -S. Chen, "A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS," 2012 Symposium on VLSI Circuits (VLSIC), 2012, pp. 92-93. [ 44 ] S. -E. Hsieh and C. -C. Hsieh, "A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1171-1175, Dec. 2016. [ 45 ] M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen and L. Fernando, "A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS," 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, pp. 153-156. [ 46 ] J. Liu, X. Tang, W. Zhao, L. Shen and N. Sun, "16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 258-260. [ 47 ] L. Shen et al., "3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 64-66. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83127 | - |
| dc.description.abstract | 為了可以以數位的方式處理信號，類比數位轉換器是自然界訊號與數位領域的重要介面。本論文提出了一個每秒一百萬次取樣的十六位元連續漸進式類比數位轉換器並使用電容誤差以及平移誤差校正。
比較器在類比數位轉換器中扮演非常重要的角色，常見的比較器架構很難達到所需的規格。環形比較器可以實現低雜訊，且可以動態調整功耗。高解析度的類比數位轉換器中的電容陣列非常大，這會使得切換電容能量效率較差。為了降低切換能量，使用了偵測與迴避切換及同步切換。此外，使用小的單位電容同樣可以有效降低切換能量，但電容誤差則是一大問題。分離式權重補償技巧可以解決該問題，而背景平移誤差校正可以處理次區間架構的平移誤差。 本文提出的類比數位轉換器在0.9伏特的供給電壓下，模擬時功耗為40.77微瓦，在加上瞬時雜訊模擬中訊號對雜訊失真比為85.49分貝，而Schreier品質因數及Walden品質因數分別為186.39dB以及每步階轉換消耗2.65飛焦耳。 | zh_TW |
| dc.description.abstract | To process the signal in the digital domain, an analog-to-digital converter (ADC) is a critical interface between the natural world and the digital domain. This thesis presents a 16-bit 1MS/s sub-ranging successive approximation register (SAR) ADC with capacitor and offset mismatch calibration.
In order to achieve 16-bit resolution, the comparator plays a critical role. It is difficult for commonly used comparator architecture to achieve the specification. The ring comparator in the fine ADC can achieve low input referred noise and dynamic saving power. The capacitor array is large in high-resolution SAR ADC, and it will cause the switching to be not energy efficient. In order to reduce the switching energy, the detect-and-skip (DAS) and aligned switching (AS) method are used. Furthermore, using a small unit capacitor can also save the switching energy, but the capacitor mismatch will become an issue. Weight-split compensation can overcome the capacitor mismatch issue, and the background offset calibration can deal with the offset mismatch in the sub-ranging architecture. In the simulation, the proposed ADC consumes 40.77uW under 0.9V supply voltage, the SNDR is 85.49dB with the transient noise, the FoMS is 186.38dB and FoMW is 2.65fj/conversion step, respectively. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-01-09T06:29:25Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-01-09T06:29:25Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
致謝 ii 摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES xi LIST OF TABLES xvi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Analog-to-Digital Converter 6 2.1 Introduction 6 2.2 Static Performance 6 2.2.1 Offset Error 6 2.2.2 Gain Error 7 2.2.3 Differential and Integral Nonlinearity 8 2.3 Dynamic Performance 9 2.3.1 Signal-to-Noise Ratio (SNR) 9 2.3.2 Total Harmonic Distortion (THD) 11 2.3.3 Spurious-Free Dynamic Range (SFDR) 11 2.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 11 2.3.5 Effective Number of Bits (ENOB) 12 2.3.6 Figure of Merit (FoM) 12 2.4 ADC Architectures 13 2.4.1 Pipeline Architecture 13 2.4.2 Two-Step and Sub-Ranging Architecture 14 2.4.3 Successive-Approximation-Register (SAR) Architecture 16 Chapter 3 High-Resolution and Low-Power SAR ADC 18 3.1 Introduction 18 3.1.1 Conventional Asynchronous SAR ADC Design 19 3.1.2 The Bottleneck of High-Resolution SAR ADC 22 3.2 High-Resolution DAC Design 23 3.2.1 Non-idealities of High-Resolution DAC 24 3.2.1.1 Sampling Noise 24 3.2.1.2 Settling Error 25 3.2.1.3 Capacitor Mismatch 26 3.2.2 Capacitor Calibration 30 3.3 Offset Mismatch Calibration 33 3.4 Comparator Design 37 3.4.1 Voltage-Domain Comparator 37 3.4.1.1 Noise 40 3.4.1.2 Offset 42 3.4.2 VCO-Based Comparator 43 3.5 Summary 49 Chapter 4 A 16-bit 1MS/s Sub-Ranging SAR ADC with Capacitor and Offset Mismatch Calibration 50 4.1 Introduction 50 4.2 Proposed Architecture 52 4.3 High-Efficiency Switching 55 4.3.1 Detect-and-Skip (DAS) Algorithm 55 4.3.2 Aligned Switching Technique 59 4.4 Weight Compensation Algorithm 61 4.4.1 Non-Skipping Weight Compensation 61 4.4.2 Weight-Split Compensation 63 4.4.3 Capacitor Calibration 66 4.5 Offset Mismatch Calibration 69 4.5.1 Digital Detection 70 4.5.2 Analog Adjustment 72 4.5.3 Digital System 77 4.6 Low Noise Ring Comparator 79 4.6.1 Ring Stage 80 4.6.2 Phase Detector 82 4.6.3 Dynamic Saving Power 83 4.7 Simulation Results 84 4.7.1 Behavior Simulation Results 84 4.7.2 Transistor Level Simulation Results 85 Chapter 5 Experiments Results 90 5.1 Measurement Environment 90 5.2 Measurement Results 91 5.3 Measurement Discussion 93 5.3.1 DFF Error 93 5.3.2 Ring Comparator Metastable 98 5.3.3 Sub-Ranging Sampling Mismatch 104 Chapter 6 Conclusions and future work 110 6.1 Conclusion 110 6.2 Future work 110 Chapter 7 Bibliography 112 | - |
| dc.language.iso | en | - |
| dc.title | 全數位校正的高解析度連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter | en |
| dc.title.alternative | All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter | - |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 郭建宏;胡耀升;鍾勇輝 | zh_TW |
| dc.contributor.oralexamcommittee | Chien-Hung Kuo;Yao-Sheng Hu;Yung-Hui Chung | en |
| dc.subject.keyword | 連續漸進式類比數位轉換器,偵測與迴避切換,同步切換,分離式權重補償,背景平移誤差校正,環形比較器, | zh_TW |
| dc.subject.keyword | successive approximation register analog-to-digital converter (SAR ADC),detect and skip (DAS),aligned switching (AS),weight split compensation,background offset calibration,ring comparator, | en |
| dc.relation.page | 119 | - |
| dc.identifier.doi | 10.6342/NTU202210043 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2022-11-16 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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