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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83124完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 莊芳懿 | zh_TW |
| dc.contributor.author | Fang-Yi Juang | en |
| dc.date.accessioned | 2023-01-09T06:28:26Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-01-06 | - |
| dc.date.issued | 2022 | - |
| dc.date.submitted | 2022-11-16 | - |
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Bruschi, "17.5 A 0.07mm2 2-channel instrumentation amplifier with 0.1% gain matching in 0.16μm CMOS," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 294-295. [41]H. Chandrakumar and D. Marković, "A 15.2-ENOB 5-kHz BW 4.5 μW Chopped CT ΔΣ -ADC for Artifact-Tolerant Neural Recording Front Ends," IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3470-3483, Dec. 2018. [42]W. -C. Wang and Y. -H. Lin, "A 0.0004% (−108dB) THD+N, 112dB-SNR, 3.15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques," IEEE International Solid-State Circuits Conference - (ISSCC), 2018, pp. 58-60. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83124 | - |
| dc.description.abstract | 隨著科技的進步，生醫訊號感測在臨床醫學診斷上日漸重要。以往須依賴大型儀器感測，而現今可透過整合系統單晶片，來達到更精準、更即時、更便利的生醫監控。而這些感測電路的主要任務為將振幅極小且低頻的信號放大，便於後端數位電路做訊號處理，為了維持訊號品質，需消除來自外界與電路本身的雜訊干擾，同時亦要求低功率與晶片面積以滿足可攜式需求。
本篇論文主要探討關於負阻抗技術對於雜訊抵銷的相關議題，因此本論文實作了兩個電路，使用製程皆為台積電180奈米製程。本篇論文提出創新之負電容抗雜訊補償技術，主要應用於生醫腦波偵測中，而負電容技術亦應用於系統的穩定度補償，主架構則選用電容耦合式儀表放大器以達成低功耗的訴求。晶片量測結果顯示，其在雜訊表現中有明顯的改善，在1到400赫茲的頻寬下，得到1.06微伏特(方均根)的等效輸入雜訊，整體雜訊被抑制約46%。另外，本論文也實作負電阻抗雜訊補償電路，其中加入了截波器技術，主要用以驗證與比較和負電容技術的差異。整體晶片核心面積僅0.494平方毫米。 | zh_TW |
| dc.description.abstract | With the evolution of technology, biomedical signal sensing is increasingly important in medical clinical diagnosis. In the past, physiological sensing had to rely on large instrument. More accurate, real-time, and convenient biomedical monitoring can be achieved with integrated SOC now. The sensing circuits are mainly used to amplify the extremely weak and low frequency signals so that the digital circuit process these signals correctly. In order to maintain signal quality, it is necessary to remove the noise interference from the outside environment and the circuit itself. For portable applications, it also requires low-power and small area performance.
In this thesis, the negative impedance technology for noise cancellation is mainly discussed, and two circuits are presented. They are both fabricated in TSMC 180-nm process. An innovative low-noise negative capacitance compensation technology for neural recording applications is proposed. The negative capacitance technology is also applied to system stability compensation. The capacitively-coupled IA (CCIA) topology is employed to achieve good power efficiency. From measurement results, it shows significant improvement in noise suppression. The input-referred noise is 1.06 uVrms from 1 to 400Hz, and the overall noise reduction is about 46%. In addition, to verify and compare with negative capacitance technology, this work also implements the negative resistance circuit with chopper technique for noise compensation. The circuit core area occupies only 0.494 mm2. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-01-09T06:28:26Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-01-09T06:28:26Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文審定書 iii
摘要 vii Abstract ix List of Figures xiii List of Tables xvii Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Overview 2 Chapter 2 Fundamental of Sensor Interface Circuits and Prior Art 5 2.1 Basic Sensor Readout Systems 5 2.2 Non-idealities in Sensor Readout Systems 10 2.2.1 Offset Voltage 10 2.2.2 Noise Response 13 2.2.3 Non-linearity 16 2.2.4 Gain Error 18 2.2.5 Common-Mode Variation 19 2.3 Dynamic Offset Compensation Technique 19 2.3.1 Auto-zeroing 20 2.3.2 Chopping 22 Chapter 3 Review of Negative Resistance Noise Cancellation Technique 25 3.1 Introduction 25 3.2 Negative Resistance System 28 3.2.1 Operation Principle 28 3.2.2 Noise Shaping 32 3.2.3 Distortion Cancellation 33 3.2.4 Effect of Mismatch 36 3.3 System Architecture 36 3.3.1 GmNR with Chopper Technique 37 3.3.2 Simulation Results 40 3.4 Discussion and Summary 43 Chapter 4 Design of a Noise-reduced CCIA with Frequency Compensation by Using Negative Capacitance Technique for Neural Recording Applications 45 4.1 Introduction 45 4.2 Motivation: Fundamental Multi-channel AFE Issue 46 4.3 Proposed CCIA with Negative Capacitance Technique 48 4.3.1 Working Principle 48 4.3.2 System Architecture 51 4.3.3 Negative Miller Technique 52 4.3.4 Programmable Pseudo-Resistor 57 4.4 Circuit Implementation 59 4.4.1 OPAMP Circuit Design 59 4.4.2 Common-Mode Feedback Circuit Design 60 4.4.3 GmNC 62 4.5 Simulation Results 67 4.6 Discussion and Summary 72 Chapter 5 Measurement Setup and Results 73 5.1 Die Photo 73 5.2 Measurement Environment Setup 73 5.3 Measurement Results 76 5.4 Summary 82 Chapter 6 Conclusions and Future Works 85 6.1 Conclusions 85 6.2 Future Works 86 References 87 | - |
| dc.language.iso | en | - |
| dc.subject | 生醫感測器 | zh_TW |
| dc.subject | 類比前端電路 | zh_TW |
| dc.subject | 截波器 | zh_TW |
| dc.subject | 腦波偵測 | zh_TW |
| dc.subject | 負電容技術 | zh_TW |
| dc.subject | 虛擬電阻 | zh_TW |
| dc.subject | 負電阻技術 | zh_TW |
| dc.subject | 低雜訊 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | Chopper | en |
| dc.subject | Analog Front-End (AFE) | en |
| dc.subject | Bio-Sensor | en |
| dc.subject | Low-Power | en |
| dc.subject | Low-Noise | en |
| dc.subject | Neural Recording | en |
| dc.subject | Negative Resistance Technique | en |
| dc.subject | Negative Capacitance Technique | en |
| dc.subject | Pseudo Resistor | en |
| dc.title | 應用於腦波偵測之低雜訊負電容耦合式前端放大器 | zh_TW |
| dc.title | A Noise-reduced CCIA with Frequency Compensation by Using Negative Capacitance Technique for Neural Recording Applications | en |
| dc.title.alternative | A Noise-reduced CCIA with Frequency Compensation by Using Negative Capacitance Technique for Neural Recording Applications | - |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 呂良鴻;蔡宗亨 | zh_TW |
| dc.contributor.oralexamcommittee | Liang-Hung Lu;Tsung-Heng Tsai | en |
| dc.subject.keyword | 類比前端電路,生醫感測器,低功率,低雜訊,腦波偵測,負電阻技術,負電容技術,虛擬電阻,截波器, | zh_TW |
| dc.subject.keyword | Analog Front-End (AFE),Bio-Sensor,Low-Power,Low-Noise,Neural Recording,Negative Resistance Technique,Negative Capacitance Technique,Pseudo Resistor,Chopper, | en |
| dc.relation.page | 92 | - |
| dc.identifier.doi | 10.6342/NTU202210048 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2022-11-17 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2027-11-01 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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