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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82650完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Hui-Ya Chen | en |
| dc.contributor.author | 陳惠雅 | zh_TW |
| dc.date.accessioned | 2022-11-25T07:48:36Z | - |
| dc.date.available | 2023-10-15 | |
| dc.date.copyright | 2021-10-21 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-10-18 | |
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Feng-Jen Chiang. (2019). All Digital Calibration for High-Resolution Successive-Approximation Register Analog-to-Digital Converter. Master Thesis, Mixed-Signal IC Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei City. Jyun-Chun Huang. (2019). A 13-bit Successive-Approximation-Register Analog-to-Digital Converter with Hybrid Reference Buffer Circuit. Master Thesis, Mixed-Signal IC Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei City. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82650 | - |
| dc.description.abstract | 連續漸進式類比至數位轉換器是一種著名的高電能效率架構由於其電容式數位至類比轉換器和低靜態功耗。然而，外圍電路的驅動是一個嚴重的問題，因此本論文提出了一種混合架構參考電壓緩衝電路，用於採用40奈米製程的0.9伏特電壓每秒一百萬次取樣的十四位元連續漸進式類比至數位轉換器。混合架構參考電壓緩衝電路包括電荷補償電路和動態參考電壓穩定器，以調節所提出的連續漸進式類比至數位轉換器之參考電壓。本文提出的類比至數位轉換器在每秒一百萬次取樣速度下，實現了11.52的測量有效位元。整體有效面積僅為0.048186平方毫米，且無需外部去耦電容。功率消耗為19.5微瓦特，品質因數達到 170.3 分貝。 此外，應用優化的可程式化繞線系統來更快地轉換電路的製程。優化的三點，包括電晶體的創建、擺置和繞線，如此一來即使是需要對稱的電路也可以完成。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T07:48:36Z (GMT). No. of bitstreams: 1 U0001-1510202116364000.pdf: 3246022 bytes, checksum: afd8f11345b30622771ec45fe59b829e (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | 口試委員會審定書 I 致謝 II 摘要 III Abstract IV Contents V List of Figures IX List of Tables XIV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of ADC with RVS and Analog Layout Generator 5 2.1 Introduction 5 2.2 Analog-to-Digital Converter 5 2.2.1 Static Performance 6 2.2.2 Dynamic Performance 9 2.2.3 Architectures 13 2.2.3.1 Pipeline 13 2.2.3.2 Two-Step and Sub-Ranging 14 2.2.3.3 Successive-Approximation-Register(SAR) 15 2.3 Reference Voltage Stabilizer (RVS) 17 2.3.1 Performance Metrics 18 2.3.1.1 Quiescent Current 18 2.3.1.2 Power Efficiency 20 2.3.1.3 Stability Analysis 21 2.3.1.4 Line Regulation and Load Regulation 22 2.3.1.5 Transient Response 24 2.3.1.6 Power Supply Rejection Ratio (PSRR) 27 2.3.2 Architectures 27 2.3.2.1 Analog LDO Regulator 28 2.3.2.2 Digital LDO Regulator 32 2.3.2.3 Analog-Assisted Digital LDO Regulator 35 2.4 Analog Layout Generator 38 2.4.1 Compilation 39 2.4.2 MOS Creation 41 2.4.3 Placement 43 2.4.4 Routing 44 2.4.4.1 Route-type 44 2.4.4.2 Options 47 Chapter 3 A 14-bit 1MS/s SAR ADC with Reference Buffer Circuit 50 3.1 Introduction 50 3.2 Proposed Architecture 52 3.3 High-Efficiency Technique 56 3.3.1 Detect-and-Skip (DAS) Algorithm 57 3.3.2 Aligned Switching Technique 60 3.3.3 Tracking Average 61 3.4 Calibration 63 3.4.1 Capacitor Calibration 63 3.4.2 Offset Mismatch Calibration 69 3.5 Switching Energy 73 3.5.1 Conventional Switching Energy 74 3.5.2 DAS Switching Energy 76 3.6 Charge Compensation (CC) 77 3.6.1 Switched Capacitor (SC) DC-DC Converter 78 3.6.2 Charge Pump and Charge Sharing Methods 79 3.6.3 Accumulated Charge Compensation (ACC) 81 3.6.4 Dual-Use Switching (DUS) 84 3.7 Dynamic Reference Voltage Stabilizer (RVS) 88 3.7.1 Proposed architecture 88 3.7.2 Stability Analysis 90 3.8 Measurement Results 95 3.8.1 Measurement Environment 97 3.8.2 Measurement Performance 99 3.8.3 Measurement discussion 108 Chapter 4 Optimized Programmable Routing in Custom IC Creator 111 4.1 Introduction 111 4.2 MOS Creation 112 4.2.1 Basic Cell 114 4.2.2 Finger and Multiplier 116 4.3 Placement 118 4.3.1 Placement Direction 118 4.3.2 Group Name 120 4.4 Routing 121 4.4.1 U-shaped Route-type 123 4.4.2 S-shaped Route-type 124 4.4.3 Options 125 4.5 Case Implementation 128 4.5.1 Compilation 130 4.5.2 Comparison 132 4.5.2.1 Symmetry 132 4.5.2.2 Common Centroid 134 4.5.2.3 Guard Ring 137 4.5.2.4 Design Time 138 Chapter 5 Conclusion and Future Work 140 5.1 Conclusion 140 5.2 Future Work 141 Bibliography 146 | |
| dc.language.iso | en | |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 可程式化繞線優化 | zh_TW |
| dc.subject | 參考電壓穩定器 | zh_TW |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 電荷補償 | zh_TW |
| dc.subject | analog-to-digital converter (ADC) | en |
| dc.subject | Optimized Programmable Routing (OPR) | en |
| dc.subject | Reference Voltage Stabilizer (RVS) | en |
| dc.subject | successive-approximation register (SAR) | en |
| dc.subject | Charge Compensation (CC) | en |
| dc.title | 一個具混合架構參考電壓緩衝電路之類比至數位轉換器與類比佈局之可程式化繞線優化 | zh_TW |
| dc.title | A Hybrid Reference Buffer Circuit for an ADC and Optimized Programmable Routing in Analog Layout | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉宗德(Hsin-Tsai Liu),蔡坤諭(Chih-Yang Tseng),洪崇智 | |
| dc.subject.keyword | 連續漸進式,類比至數位轉換器,電荷補償,參考電壓穩定器,可程式化繞線優化, | zh_TW |
| dc.subject.keyword | successive-approximation register (SAR),analog-to-digital converter (ADC),Charge Compensation (CC),Reference Voltage Stabilizer (RVS),Optimized Programmable Routing (OPR), | en |
| dc.relation.page | 153 | |
| dc.identifier.doi | 10.6342/NTU202103761 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2021-10-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2023-10-15 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| U0001-1510202116364000.pdf 授權僅限NTU校內IP使用（校園外請利用VPN校外連線服務） | 3.17 MB | Adobe PDF |
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