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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Chun-Hung Yu | en |
| dc.contributor.author | 游雋閎 | zh_TW |
| dc.date.accessioned | 2022-11-25T06:32:50Z | - |
| dc.date.copyright | 2022-03-02 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-02-14 | |
| dc.identifier.citation | USB 3.0 Promoter Group, 'The USB 3.2 Specification,' 17 September 2017. Accessed on: May 20, 2021. [Online]. Available: https://www.usb.org/document-library/usb-32-specification-released-september-22-2017-and-ecns. J. Lee, K. S. Kundert, and B. Razavi, 'Analysis and modeling of bang-bang clock and data recovery circuits,' IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sep. 2004. D. Hong and K. T. Cheng, 'Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links,' in Proc. 26th IEEE VLSI Test Symp., May 2008, pp. 17-22. C. He and T. Kwasniewski, 'Bang-Bang CDR’s acquisition, locking, and jitter tolerance,' in Proc. IEEE Canadian Conf. Electrical Comp. Engineering, Apr. 2012, pp. 1-4. Y. Sun and H. Wang, 'Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers,' in Proc. IEEE Custom Integr. Circuits Conf. (CICC), San Jose, U.S.A, Sep. 2009, pp 343-346. S. Erb and W. Pribyl, 'A method for fast jitter tolerance analysis of high-speed PLLs,' in Design, Automation and Test in Europe., Grenoble France, 2011, pp. 1-6. Y. L. Lee, Y. P. Cheng, S. J. Chang, and H. W. Ting, 'A fast and jitter modulation free jitter tolerance estimation technique for bang-bang CDRs,' IEEE Design Test, vol. 35, no. 1, pp. 63-73, Sep. 2018. IEEE Standard for Jitter and Phase Noise, IEEE Std 2414-2020, 26 Feb. 2021. S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs. Hoboken, N.J.: Wiley, 2009. A. Amirkhany, 'Basics of clock and data recovery circuits: exploring high-speed serial links,' IEEE Solid-State Circuits Mag., vol. 12, no. 1, pp. 25-38, Jan. 2020, doi: 10.1109/MSSC.2019.2939342. Y. Duan and D. Chen, 'Fast and accurate decomposition of deterministic jitter components in high-speed links,' IEEE Trans. Electromagn. Compat., vol. 61, no. 1, pp. 217-225, Feb. 2019. J. Galloway, 'Why Do We Need SERDES?,' 22 May 2020. [Online]. Available: https://www.electronicdesign.com/technologies/analog/article/21132088/why-do-we-need-serdes. [Accessed 15 7 2021]. B. Razavi, 'Chapter 9: clock and data recovery,' in Design of Integrated Circuits for Optical Communications, 2nd Edition, WILEY, 2012. F. M. Gardner, 'Chapter 2: transfer functions of analog PLLs,' in Phaselock Techniques, 3rd Edition, John Wiley Sons, Inc., 2005. V. Macaitis, R. Navickas, 'Design of high frequency, low phase noise LC digitally controlled oscillator for 5G intelligent transport systems,' Electronics, p. https://doi.org/10.3390/electronics8010072, 8 Jan. 2019. J. A. Tierno, A. V. Rylyakov and D. J. Friedman, 'A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,' IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008. Tektronix, 'USB 3.1 Receiver Compliance Testing Application Note,' 1 2015. Accessed on: Oct. 6, 2020. [Online]. Available: https://download.tek.com/document/55W-26804-2%20USB%203.1%20Receiver%20Compliance%20Testing%20AN.pdf. E. Cheng, J. Kho, Y. L. Tan, W. W. Lo and M. O. Wong, 'Jump the Q: A fast jitter tolerance measurement method using Q-statistical model,' in Proc. IEEE Elect. Des. Adv. Packag. Syst. Symp., Dec. 2010, pp. 1–4. H. Zhang, Fa. Rao, D. (Z.) Wu, and G. Zhang, 'IBIS-AMI modeling of asynchronous high speed link systems,' in DesignCon, Santa Clara, CA, USA, 2017. Tektronix, 'USB 3.1 Receiver Compliance Testing Application Note,' 1 2015. Accessed on: Oct. 6, 2020. [Online]. Available: https://download.tek.com/document/55W-26804-2%20USB%203.1%20Receiver%20Compliance%20Testing%20AN.pdf. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82147 | - |
| dc.description.abstract | "對於一個高速串列解串系統，通常會用訊號抖動容忍度測試來評估接收電路的性能，它是在測試訊號中加入正弦抖動、符碼間干擾抖動以及隨機抖動來測試接收電路在極端條件下的誤碼率。然而，訊號抖動容忍度測試的儀器非常昂貴，模擬也因為需要逐位元分析而極為耗時。過去有研究提出一些適用於接收電路中時鐘數據恢復電路的抖動容忍度預測方法，但這些方法都因為沒有考慮訊號通道頻寬限制所造成的符碼間干擾抖動，而無法被應用於實際的串列解串系統。 此篇論文擴展了過去的逐位元分析預測法，透過整合進一個時域的符碼間干擾抖動模型及改進時鐘數據恢復電路的相位行為模型，來突破過去方法無法使用於串列解串系統的限制，並藉助兩個運算上的加速技巧，所提出的預測方法在速度上可以比模擬快90,000倍，同時仍保持很低的誤差。接著，此篇論文再提出一個可以進一步降低耗時的外插技巧，他是基於計算錯誤位元數的期望值，以利用較少的位元分析數量來預測更低誤碼率要求下的抖動容忍度，使用這項外插技巧的預測可以比原先的完整位元分析預測再快4,000倍，其預測結果只有百分之六的偏差，透過所提出的預測方法，九個不同正弦抖動頻率在1E-10誤碼率要求下的抖動容忍度可以在七秒鐘內被預測，所需時間比量測快120倍。 此篇論文也將提出的方法應用在實際的USB訊號抖動容忍度測試量測實驗，藉由合成出的等效時鐘數據恢復電路來作訊號抖動容忍度預測，並與量測結果作比較。有部分預測準確性欠佳，在論文最後有討論可能的誤差原因及實驗中的不確定因素，並提出對未來實驗的建議。 " | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T06:32:50Z (GMT). No. of bitstreams: 1 U0001-1302202211095500.pdf: 7974963 bytes, checksum: 0e7976e7a11a4544cb28a943f1b6b368 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | "CONTENTS 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 1 1.3 Contributions 3 1.4 Organization of this thesis 4 Chapter 2 Background Knowledge of SerDes Systems 5 2.1 Introduction of Timing Jitter 5 2.1.1 Random Jitter (RJ) 6 2.1.2 Sinusoidal Jitter (SJ) 7 2.1.3 Intersymbol Interference (ISI) Induced Jitter 8 2.2 Introduction of High-Speed SerDes Systems 9 2.3 Clock and Data Recovery (CDRs) in High-Speed SerDes Receiver 12 2.3.1 Basic Architecture and Operational Mechanism of CDRs 12 2.3.2 Introduction of Bang-Bang CDRs (BBCDRs) 14 2.3.3 Jitter Tolerance (JTOL) Test 19 2.4 Previous Fast jitter tolerance estimation for bang-bang CDRs 22 2.4.1 Stage 1: Tracking Capability 23 2.4.2 Stage 2: JTOL Estimation with Tracking Capabilities 24 2.4.3 Random Jitter (RJ) Consideration 26 2.4.4 Estimation Result and Summary 27 Chapter 3 Proposed JTOL Estimation Method 30 3.1 Used Architecture of the Serial Link and CDR Phase Behavior Model 30 3.2 Structure of Proposed JTOL Estimation Method 34 3.3 ISI jitter and Random Jitter (RJ) Modeling 37 3.3.1 ISI jitter Modeling 37 3.3.2 Random Jitter Modeling 41 3.4 Acceleration Techniques for Proposed Estimation 42 3.4.1 Parallel Computing 42 3.4.2 Two-Stage Estimation 43 3.5 Estimation Results and Verifications with Simulation 44 3.5.1 JTOL test Environment and Simulation Model 44 3.5.2 ISI jitter modeling 46 3.5.3 Result Comparison between Estimation and Simulation 48 3.5.4 JTOL Test Estimation at ultra-Low BER 51 3.6 Summary 53 Chapter 4 Proposed Extrapolation Technique for Ultra-Low BER Requirements 54 4.1 The Influence of BER Requirements on the JTOL Test 54 4.1.1 Data Transition Rate Variety 55 4.1.2 Frequency Difference for SJ 56 4.1.3 ISI Jitter 57 4.1.4 Random Jitter 58 4.1.5 Summary 59 4.2 Extrapolated JTOL Estimation with Expected Value of BER 60 4.3 Extrapolated Estimation Result Verification 65 4.4 Summary 68 Chapter 5 Measuring Experiment of the JTOL Test 69 5.1 The Environment and Process of the USB 3.1 Gen 2 JTOL Test 69 5.1.1 The Environment of the JTOL Test 69 5.1.2 The Process of the JTOL Test 71 5.2 Experiment Plan and Measurement Results 72 5.2.1 Proposed Process Flow of the Measurement Experiment 72 5.2.2 Measurement Equipment Setup 73 5.2.3 Measurement Results 74 5.3 ISI Jitter Modeling and CDR Synthesis 75 5.3.1 ISI Jitter Model Generation 75 5.3.2 CDR Synthesis 80 5.4 JTOL Estimation with Synthesized CDR 84 5.5 Summary 87 Chapter 6 Conclusions 88 6.1 Conclusions of this Thesis 88 6.2 Suggestions of Future Works 89 REFERENCE 91 LIST OF FIGURES Fig. 2.1. Example of timing jitter caused by additive amplitude noise. [8] 5 Fig. 2.2. The categories of the jitters. [9] 6 Fig. 2.3. An example PDF of RJ with σ=1 ps in (a)linear scale and (b)log scale. [9] 7 Fig. 2.4. (a) The pulse response of an example channel. (b) An example for ISI induced jitter. 8 Fig. 2.5. A typical CDR-based SerDes system building blocks. SER: serializer; PLL: phase-lock-loop; AFE: analog front end; CDR: clock and data recovery; DESER: deserializer. [10] 10 Fig. 2.6. A typical forwarded-clock system. [10] 11 Fig. 2.7. A basic CDR architecture. VCO: voltage-controlled oscillator. [10] 12 Fig. 2.8. An example waveform of the data and clock with jitter. [10] 14 Fig. 2.9. A digital bang-bang CDR. BBPD: bang-bang phase detector, DCO: digital control oscillator. [10] 15 Fig. 2.10. (a) Three-point sampling of data by the clock. (b) Configuration of Alexander phase detector. (c) Waveforms of a “clock early” example. [11] 16 Fig. 2.11. (a) A simple analog loop filter of a second-order type-II CDR, and (b) its equivalent circuit in s-domain. (c) A digital P-I loop filter of a second-order type-II CDR. [12] 18 Fig. 2.12. (a) Jitter tolerance (JTOL) test procedure flow graph. (b) JTOL result plot. (c) a JTOL measurement setup. [2] 20 Fig. 2.13. The digital CDR architecture and test circuits in [7]. 23 Fig. 2.14. The tracking capability of KP and KI in digital CDRs. [7] 24 Fig. 2.15. The estimated JTOL curves and the difference between the estimated and simulated results at BER = 10-5 are depicted for (a) case 1 and (b) case 2. [7] 28 Fig. 3.1. The focused serial link part in the SerDes system in the JTOL test. [10] 31 Fig. 3.2. (a) The used second-order type-2 CDR architecture. (b) The CDR phase behavior model. 33 Fig. 3.3. The process of a full JTOL test. 34 Fig. 3.4. The flow chart of the proposed JTOL estimation method. 36 Fig. 3.5. An example pulse response of a channel for m=4. [15] 38 Fig. 3.6. The process of building an ISI jitter table. [15] 38 Fig. 3.7. (a) The effect of the pre-cursor on the ISI. (b) Bit-flipping cases have equal ISI jitter values. (c) Directly generate the waveform of each bit pattern for ISI jitter estimation. 40 Fig. 3.8. The process flow of ISI jitter regeneration. 40 Fig. 3.9. An example of parallel computing for JTOL estimation. 42 Fig. 3.10. Two-stage JTOL estimation. (a) Stage 1: 10 % bit length with rough step. (b) full test data with precise steps. 43 Fig. 3.11. (a) The physical structure of the microstrip line. (b) The S21 parameters of three different channels. (c) The eye diagram of the 20 cm and (d) 40 cm microstrip. 45 Fig. 3.12. The block model of the Simulink JTOL test simulation. 46 Fig. 3.13. The ISI jitter model of (a) 20 cm and (b) 40 cm microstrip line. 47 Fig. 3.14. (a) Example for ISI jitter model with redundant n. (b) The RMS of symmetrical deviation for different m. 48 Fig. 3.15. JTOL result comparison between estimation and simulation for (a) CDR 1 without RJ, (c) CDR 1 with RJ, and (e) CDR 2 with RJ. (b)(d)(f) The corresponding estimation error for each case. 49 Fig. 3.16. (a) JTOL estimation at different BER. (b) Estimated JTOL drop compares to BER = 1E-5 case. 51 Fig. 4.1. Estimated JTOL performance drop applying only SJ at different BER requirements compared to BER = 1E-5 case with (a) CDR1 and (b) CDR 2. The traces for BER = 1E-7, 1E-8, and 1E-9 cases overlap with the trace for BER = 1E-10. 56 Fig. 4.2. Estimated JTOL performance drop with SJ and ISI jitter at different BER requirements compared to BER = 1E-5 case with (a) CDR1 and (b) CDR 2. The traces for BER = 1E-7, 1E-8, and 1E-9 cases overlap with the trace for BER = 1E-10. 58 Fig. 4.3. Estimated JTOL performance drop with SJ and RJ at different BER requirements compared to BER = 1E-5 case with (a) CDR1 and (b) CDR 2. 59 Fig. 4.4. The probability for RJ exceeding rUB. 61 Fig. 4.5. The flow chart of the proposed JTOL estimation with extrapolation. 64 Fig. 4.6. Extrapolated estimation deviations from (a) 1E7 bits and (b) 1E6 bits compared to the full-bit estimation. 66 Fig. 4.7. (a) Comparison of extrapolated and full-bit JTOL Estimation with different RJ values. (b) The JTOL drop compares to the 1 ps RJ case at 1E-9 BER requirement. 67 Fig. 5.1 USB 3.1 Gen 2 receiver compliance test configuration. 70 Fig. 5.2. The calibration setup of USB 3.1 Gen 2 JTOL test. 71 Fig. 5.3. The process flow of the measurement experiment. 73 Fig. 5.4. The equipment setup of the measurement. 74 Fig. 5.5. The measurement result of the USB 3.1 Gen 2 JTOL test with different channels. 75 Fig. 5.6. The setup block diagram in the simulation for (a) calibration and (b) ISI waveform generation. 76 Fig. 5.7. The eye diagram of (a) uncalibrated channel and (b) calibrated channel. 77 Fig. 5.8. The eye diagrams before and after the CTLE for (a) 0 dB, (b) -14 dB, and (c) -17 dB channels. 79 Fig. 5.9. (a) The RMS of the adjacent pair jitter deviation for n determination. (b) The RMS of the symmetrical pair jitter deviation for m determination. 80 Fig. 5.10. The ISI jitter model for (a) 0 dB, (b) -14 dB, and (c) -17 dB channels. 80 Fig. 5.11. KP sweeping for KP/KI=200. 81 Fig. 5.12. The CDR fitting errors for phase error margin = (a) 0.45, (b) 0.40, (c) 0.38, or (d) 0.36 UI. Each phase error margin case has three-stage parameters sweeping. 82 Fig. 5.13. (a) JTOL estimation of the synthesized CDRs with -14 dB channel. (b) The fitting errors with -14 dB channel for different phase error margin cases. 83 Fig. 5.14. The JTOL estimation with synthesized CDRs and its estimation errors for (a) 0 dB and (b) -17 dB channels. 84 Fig. 5.15. The JTOL comparison between the -17 dB internal ISI and -14 dB internal ISI with the cascading USB channel board. 86 Fig. 6.1. The recommended setup for measurement experiment. 90 LIST OF TABLES Table 2.1. The relationship between BER and peak-to-peak RJ [7] 26 Table 2.2. CDR Parameters and Test Conditions [7] 27 Table 3.1. Design parameters of the serial links. 44 Table 3.2. The added jitter in the JTOL test. 45 Table 3.3. The time of the proposed estimation and simulation under BER = 1E-5. 51 Table 3.4. The time cost comparison between JTOL estimation, simulation, and measurement at different BER. 52 Table 4.1. The time costs of different estimation techniques at each BER requirement. 68 Table 5.1. JTOL test conditions for USB 3.1 Gen 2. 70 Table 5.2. Specification of the stressed eye calibration. 71 Table 5.3. The CTLE pre-set gain of the receiver IBIS-AMI model. 77 Table 5.4. The minimum-error CDR parameters for the sweeping. 82 Table 5.5. Maximum fitting error for different phase error margins. 83 " | |
| dc.language.iso | en | |
| dc.subject | 時間數據恢復電路 | zh_TW |
| dc.subject | 串列解串系統 | zh_TW |
| dc.subject | 訊號抖動 | zh_TW |
| dc.subject | 誤碼率 | zh_TW |
| dc.subject | CDR circuits | en |
| dc.subject | SerDes | en |
| dc.subject | jitter | en |
| dc.subject | bit-error-rate (BER) | en |
| dc.title | 高速串列解串系統訊號抖動容忍度的快速預測 | zh_TW |
| dc.title | A Fast Estimation for Jitter Tolerance in High-Speed SerDes Systems | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Ren-Guey Lee),王挺光(Sung-Nien Yu),鄭齊軒(Hen-Wai Tsao),(Yi-Chang Lu),(Ming-Der Shieh),(Ming-Der Shieh),(Ming-Der Shieh) | |
| dc.subject.keyword | 串列解串系統,訊號抖動,誤碼率,時間數據恢復電路, | zh_TW |
| dc.subject.keyword | SerDes,jitter,bit-error-rate (BER),CDR circuits, | en |
| dc.relation.page | 93 | |
| dc.identifier.doi | 10.6342/NTU202200583 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2022-02-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2024-02-14 | - |
| 顯示於系所單位： | 電信工程學研究所 | |
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