請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82082完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳銘憲(Ming-Syan Chen) | |
| dc.contributor.author | Chia-Chen Yen | en |
| dc.contributor.author | 嚴家成 | zh_TW |
| dc.date.accessioned | 2022-11-25T05:35:29Z | - |
| dc.date.available | 2027-02-10 | |
| dc.date.copyright | 2022-03-02 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-02-12 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82082 | - |
| dc.description.abstract | 數位訊號處理(DSP)在現今電子系統如行動通信、自駕車控制單元等扮演著重要的角色。其中廣泛使用的計算作業為多常數乘法(MCMs)，使用的情境包含有數位濾波器與離散轉換。在特定應用積體電路(ASIC)廣泛運用的同時，有越來越多的高性能數位訊號處理系被大量實作於現場可程式化邏輯閘陣列晶片(FPGAs)中，這使得許多研究專注在簡化多常數乘法器的複雜度。然而因現場可程式化邏輯閘陣列晶片本身計算資源的限制，當這些數位訊號處理應用程式在使用多常數乘法作業時，需要頻繁地重置加速器內部的乘法係數，然而至今仍沒有相關的研究專注在一致性硬體拓撲的前提下發展多常數乘法器，來避免耗時的重置時間。此外，這些數位訊號處理系統通常需要可提供高度平行化的記憶體架構來保證它們對資料存取的一致性，雖然現今的現場可程式化邏輯閘陣列晶片提供了雙埠記憶體區塊，但若將這些記憶體區塊實作成多埠記憶體來提供平行化的存取，將會造成大量的記憶體消耗。 在本論文中，我們針對需要頻繁重置乘法器區塊的應用程式提出了一個名為一元化多常數乘法(UMCM)的問題，並同時提出了一個名為兼容性之圖合成的平台，來有效率地建構一元化多常數乘法器。在該平台中，僅靠一組對數位移器之參數集，即可快速地動態重置乘法器區塊中的係數，避免使用現場可程式化邏輯閘陣列晶片所提供的重置技術，而增加系統的回應時間。根據實驗結果顯示，我們所提出的一元化多常數乘法技術非常適用於因硬體計算資源限制而需要頻繁重置乘法器的數位訊號處理應用程式。 此外，為了確保這些數位訊號處理系統擁有對資料存取的一致性，在本論文中，我們同樣提出了一種可支援多埠切換的平行化記憶體存取架構，稱之為IMPC，來解決大量的記憶體與邏輯單元消耗的問題。該架構預先定義好一組軟/硬式存取埠的記憶體單元，再利用最小集合配置(MSP)問題來尋找一組使用最少記憶體單元的組合，來達到上述目的，根據實驗結果顯示，我們所提出的可支援多埠切換的記憶體存取架構可有效降低記憶體與相關計算資源的消耗。 | zh_TW |
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| dc.description.tableofcontents | 誌謝 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Goal and Contributions of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Preliminary Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Basic Logic Elements (BLEs) in Xilinx FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 Block Random Access Memories in FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Constant Multiplications on FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Single Constant Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1.1 Binary Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1.2 Multiplication using Signed Digit Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 Multiple Constant Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2.1 Adder Graph Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2.2 The MCM Problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2.3 Mapping of Adder Graphs to FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 RAM Multi-Porting Distribution Techniques on FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1 Multi-Read BRAM: Bank Replication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.2 Multi-Write RAM: MultiBanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.3 Time-Multiplexing RAM: MultiPumping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 Unified Multiple Constant Multipliers for Dynamic Exchange of Low-Precision Kernels on FPGAs . . . . . . . . 27 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 Preliminary and Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.1 Adder Graph Representation of Multiplier Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.2 Odd Fundamental Graph Transformation The MCM Framework . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.3 Bull-Horrocks algorithm (BHA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.4 Bull-Horrocks modified algorithm (BHM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.5 n-Dimensional reduced adder graph (RAGn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.6 Heuristic basedon Cumulative Benefit (Hcub). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 The Unified MCM Problem and The Compatible Graph Synthesis Framework . . . . . . . . . . . . . . . . . . . 38 3.3.0.1 Equivalent Index Evaluation (EIE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.0.2 Congruous Interpolation (CI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.1 Agraph Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.2 Multiplication Time Overhead and Average Throughput. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.3 Partial Reconfiguration Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 Integrated Multi-Ported Memory Distribution for Temporal/Spatial-Multiplexing Parallel Workloads on FPGAs. . 50 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 Preliminary and Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.1 Temporal/SpatialMultiplexing Parallel Workloads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.2 Conventional MultiPorted BRAM Distribution Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2.1 Uni-directional Distribution Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2.2 Bi-directional Distribution Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.2.3 Multi-Switched-Porting Distribution Scheme (MSPDS) . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.3 Hard/Soft Porting BRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2.4 Graph Modelling for Uni/Bidirectional Schemes and MSPDS. . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3 Integrated Multi-Porting Configuration for BRAM Distribution . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.1 Write/Read Coexistence Graph with (pq)-Cliques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.2 Integrated Multi-Porting Optimization on WRCG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.1 Analysis of BRAM Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.2 Space Analysis - Number of Occupied LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 | |
| dc.language.iso | en | |
| dc.subject | 多埠記憶體 | zh_TW |
| dc.subject | 現場可程式化邏輯閘陣列 | zh_TW |
| dc.subject | 多常數乘法 | zh_TW |
| dc.subject | 一元化多常數乘法 | zh_TW |
| dc.subject | FPGA | en |
| dc.subject | MCM | en |
| dc.subject | UMCM | en |
| dc.subject | Multi-Ported Memory | en |
| dc.title | 植基於現場可程式化邏輯閘陣列晶片之高效重置乘法器與集成型記憶體分配架構 | zh_TW |
| dc.title | Effective Reconfigurable Multiplication and Integrated Memory Distribution on FPGAs | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.author-orcid | 0000-0002-4286-4806 | |
| dc.contributor.oralexamcommittee | 葉彌妍(Yi-Chen Lo),張原豪(Bu-Miin Huang),修丕承(Ching-Chuan Kuo),賴冠廷(Yuan-Soon Ho) | |
| dc.subject.keyword | 現場可程式化邏輯閘陣列,多常數乘法,一元化多常數乘法,多埠記憶體, | zh_TW |
| dc.subject.keyword | FPGA,MCM,UMCM,Multi-Ported Memory, | en |
| dc.relation.page | 90 | |
| dc.identifier.doi | 10.6342/NTU202200528 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-02-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2027-02-14 | - |
| 顯示於系所單位： | 電機工程學系 | |
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|---|---|---|---|
| U0001-1002202214223600.pdf 未授權公開取用 | 4.02 MB | Adobe PDF | 檢視/開啟 |
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