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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82079完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 廖世偉(Shih-Wei Liao) | |
| dc.contributor.author | Song-Lin Wu | en |
| dc.contributor.author | 吳松霖 | zh_TW |
| dc.date.accessioned | 2022-11-25T05:35:25Z | - |
| dc.date.available | 2027-01-06 | |
| dc.date.copyright | 2022-02-24 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2022-01-11 | |
| dc.identifier.citation | [1] Mkl: Math kernel library : https://github.com/oneapisrc/onemkl. [2] Mlirhlo: A standalone ”hlo” mlirbased compiler : https://github.com/tensorflow/ mlirhlo. [3] Mlirx: https://github.com/polymagelabs/mlirx. [4] Openvx 1.3 spec: https:// www.khronos.org/ registry/ openvx/ specs/ 1.3/ openvx_specification_1_3.pdf. [5] Openvx: https://www.khronos.org/openvx. [6] M. Abadi, P. Barham, J. Chen, Z. Chen, A. Davis, J. Dean, M. Devin, S. Ghe mawat, G. Irving, M. Isard, M. Kudlur, J. Levenberg, R. Monga, S. Moore, D. G. Murray, B. Steiner, P. Tucker, V. Vasudevan, P. Warden, M. Wicke, Y. Yu, and X. Zheng. Tensorflow: A system for largescale machine learning. In 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI 16), pages 265–283, 2016. [7] R.Baghdadi,J.Ray,M.B.Romdhane,E.D.Sozzo,A.Akkas,Y.Zhang,P.Suriana, S. Kamil, and S. Amarasinghe. Tiramisu: A polyhedral compiler for expressing fast and portable code, 2018. [8] C. Bastoul. Code generation in the polyhedral model is easier than you think. In PACT’13 IEEE International Conference on Parallel Architecture and Compilation Techniques, pages 7–16, JuanlesPins, France, September 2004. [9] M.W. Benabderrahmane, L.N. Pouchet, A. Cohen, and C. Bastoul. The polyhe dral model is more widely applicable than you think. In R. Gupta, editor, Compiler Construction, pages 283–303, Berlin, Heidelberg, 2010. Springer Berlin Heidelberg. [10] U. Bondhugula. High performance code generation in MLIR: an early case study with GEMM. CoRR, abs/2003.00532, 2020. [11] K. Goto and R. A. v. d. Geijn. Anatomy of highperformance matrix multiplication. ACM Trans. Math. Softw., 34(3), May 2008. [12] A. Hartono, M. M. Baskaran, C. Bastoul, A. Cohen, S. Krishnamoorthy, B. Nor ris, J. Ramanujam, and P. Sadayappan. Parametric multilevel tiling of imper fectly nested loops. In Proceedings of the 23rd International Conference on Supercomputing, ICS ’09, page 147–157, New York, NY, USA, 2009. Association for Computing Machinery. [13] A. Krizhevsky, I. Sutskever, and G. E. Hinton. Imagenet classification with deep convolutional neural networks. Commun. ACM, 60(6):84–90, May 2017. [14] C. Lattner, M. Amini, U. Bondhugula, A. Cohen, A. Davis, J. Pienaar, R. Riddle, T. Shpeisman, N. Vasilache, and O. Zinenko. Mlir: Scaling compiler infrastructure for domain specific computation. In 2021 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pages 2–14, 2021. [15] S. Maleki, Y. Gao, M. J. Garzar ́n, T. Wong, and D. A. Padua. An evaluation of vectorizing compilers. In 2011 International Conference on Parallel Architectures and Compilation Techniques, pages 372–382, 2011. [16] J. RaganKelley, C. Barnes, A. Adams, S. Paris, F. Durand, and S. Amarasinghe. Halide: A language and compiler for optimizing parallelism, locality, and recompu tation in image processing pipelines. In Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI ’13, page 519–530, New York, NY, USA, 2013. Association for Computing Machinery. [17] S. Tavarageri, A. Hartono, M. Baskaran, L.N. Pouchet, J. Ramanujam, and P. Sa dayappan. Parametric tiling of affine loop nests. In Proc. 15th Workshop on Compilers for Parallel Computers. Vienna, Austria, 2010. [18] S. Verdoolaege. Isl: An integer set library for the polyhedral model. In Proceedings of the Third International Congress Conference on Mathematical Software, ICMS’10, page 299–302, Berlin, Heidelberg, 2010. SpringerVerlag. [19] Q. Wang, X. Zhang, Y. Zhang, and Q. Yi. Augem: Automatically generate high performance dense linear algebra kernels on x86 cpus. In SC ’13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, pages 1–12, 2013. [20] Z. Xianyi, W. Qian, and Z. Yunquan. Modeldriven level 3 blas performance opti mization on loongson 3a processor. In 2012 IEEE 18th International Conference on Parallel and Distributed Systems, pages 684–691, 2012. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/82079 | - |
| dc.description.abstract | 在過去數年中，相機為主的應用佔據手機應用程式中相當大的一部分，主要是因為社群軟體與AI整合的應用程式頻繁的出現。任何具有一定程式能力的人在沒有影像處理的知識，甚至完全沒有相關知識的情況下都可以利用網路上許多傑出的框架與工具快速地建立屬於自己的模型，因此迅速的推動此類應用的發展， 然而每個框架都有其優劣，所以目前尚未有一個「最」具代表性的優勝者。 OpenVX是一個針對電腦視覺應用而開發的框架，它具有可攜性並且可針對不同的架構做客製化的實現，在現今的主流異構架構中，佔有相當的地位。在這篇論文中，我們將探討如何利用不同語言與框架來加速 OpenVX。 MLIR 是一個編譯器框架，此框架具有很多客製化的「方言」，用來做不同 的程式架構表達，並且可以利用這些方言搭配手寫的程式碼轉換邏輯對程式進 行優化。Halide 是一個在影像處理領域相當突出的語言，它將「演算法」與「排 程」分開處理與優化，因此相當大程度的增加優化彈性與效率，目前也被 Google 的 Pixel 採納用來做相機的影像處理。為了生成更有效率的程式碼，我們提出了' Bridge“，一個可以將 OpenVX 轉換成 Halide 和 MLIR 的系統。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-25T05:35:25Z (GMT). No. of bitstreams: 1 U0001-2209202121351600.pdf: 5888031 bytes, checksum: 9a744452207e5ffa9cd663e54fce2aa8 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | Verification Letter from the Oral Examination Commitee i Acknowledgements. ii 摘要 iii Abstract iv Contents vi List of Figures viii List of Tables. x Chapter 1 Introduction 1 Chapter 2 Background 3 2.1 OpenVX 3 2.2 Halide 4 2.3 MLIR 6 2.4 Affine Transformation 7 Chapter 3 Motivation 10 Chapter 4 Design and Implementation 11 4.1 OpenVX Transformation 12 4.1.1 OpenVX to MLIR 12 4.1.1.1 Memory Reference(MemRef) 12 4.1.1.2 Affine Representation 13 4.1.1.3 Affine loop tiling 16 4.1.1.4 Vectorization 16 4.1.2 OpenVX to Halide. 18 4.2 Halide Conversion 19 4.2.1 Halide Runtime Library Translator 23 Chapter 5 Evaluation and Discussion 26 5.1 Environment Setup 26 5.2 Experiment Steps 27 5.3 Result 27 5.4 Discussion 30 Chapter 6 Future Work. 31 Chapter 7 Conclusion 32 References 33 | |
| dc.language.iso | en | |
| dc.subject | 影像處理 | zh_TW |
| dc.subject | Halide | zh_TW |
| dc.subject | MLIR | zh_TW |
| dc.subject | OpenVX | zh_TW |
| dc.subject | Halide | en |
| dc.subject | ImageProcessing | en |
| dc.subject | OpenVX | en |
| dc.subject | MLIR | en |
| dc.title | 利用 Halide 與 MLIR 加速 OpenVX | zh_TW |
| dc.title | Accelerating OpenVX through Halide and MLIR | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張傑帆(Hsin-Tsai Liu),陳鵬升(Chih-Yang Tseng),傅楸善,關啟邦 | |
| dc.subject.keyword | Halide,MLIR,OpenVX,影像處理, | zh_TW |
| dc.subject.keyword | Halide,MLIR,OpenVX,ImageProcessing, | en |
| dc.relation.page | 35 | |
| dc.identifier.doi | 10.6342/NTU202103297 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-01-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
| dc.date.embargo-lift | 2027-01-06 | - |
| 顯示於系所單位： | 資訊網路與多媒體研究所 | |
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