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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81725完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為(Chee Wee Liu) | |
| dc.contributor.author | Shih-Ya Lin | en |
| dc.contributor.author | 林詩雅 | zh_TW |
| dc.date.accessioned | 2022-11-24T09:26:20Z | - |
| dc.date.available | 2022-11-24T09:26:20Z | - |
| dc.date.copyright | 2022-01-17 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-12-12 | |
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Barraud et al., “Performance and design considerations for gate-all-around stacked-NanoWires FETs,“ in 2017 IEEE international electron devices meeting (IEDM), 2017, pp. 29.2.1-29.2.4. [156] Y.-C. Fu et al., “High mobility high on/off ratio CV dispersion-free Ge n-MOSFETs and their strain response,“ in 2010 International Electron Devices Meeting, 2010, pp. 18.5.1-18.5.4. [157] Y.-J. Yang, W. Ho, C.-F. Huang, S. Chang, and C. Liu, “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, vol. 91, no. 10, p. 102103, 2007. [158] I.-H. Wong et al., “High performance Ge junctionless gate-all-around NFETs with simultaneous Ion= 1235 μA/μm at Vov= Vds= 1V, SS= 95 mV/dec, high Ion/Ioff= 2×106, and reduced noise power density using S/D dopant recovery by selective laser annealing,“ in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 33.6.1-33.6.4. [159] I.-H. Wong et al., “In-situ doped and tensily stained ge junctionless gate-all-around nFETs on SOI featuring Ion= 828 μA/μm, Ion/Ioff ∼ 1×105, DIBL= 16–54 mV/V, and 1.4X external strain enhancement,“ in 2014 IEEE International Electron Devices Meeting, 2014, pp. 9.6.1-9.6.4. [160] E. Capogreco et al., “First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs,” IEEE Transactions o……… | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81725 | - |
| dc.description.abstract | 隨著技術節點的發展，擁有相較於矽材料更高載子遷移率之鍺矽、鍺、鍺錫等四族半導體材料被視為極可能取代業界現行矽材料之新興材料，其具有下列優點，包含：相較於矽擁有更高載子遷移率使元件電性表現相較傳統矽材料更好、可實現直接能隙、可與傳統矽製程技術相容等，使其能應用於高速運算電路及光學元件等相關領域中。在本論文中，將使用化學氣相沉積進行四族材料磊晶成長、材料分析、熱穩定性及錫析出特性之研究與探討。此外，本論文亦探討化學氣相沉積成長之鍺錫接面二極體之製備與特性分析，以及透過紅外光響應方式檢測垂直堆疊鍺矽n 型閘極環繞式電晶體之寄生通道特性。 在本論文的第一個部分，鍺材料之選擇性成長被首先探討。鍺具有最高的電洞遷移率，且其於近紅外光波段之吸收常數相當高，因此，無論是互補式氧化金屬半導體技術或紅外光電材料元件，例如CMOS 影像感測器，鍺材料均是最佳首選。但由於鍺和矽之間具有4.2%的晶格不匹配，鍺材料直接成長於矽材料上會導致相當大的差排缺陷密度。而降低差排缺陷密度的方法有成長矽鍺漸變濃度緩衝層、循環熱退火、及選擇性成長等。其中選擇性成長的應用，除了可以用以降低差排缺陷密度之外，亦可用來同時整合高電洞遷移率之鍺通道材料及高電子遷移率之矽材料於同一基板上。透過化學氣象沉積方法來達到高選擇比鍺材料選擇性成長將在此論文被研究，而結晶品質不佳與貫穿差排的問題，則可透過高溫磊晶後熱退火來加以改善。 本論文的第二個部分，主要針對鍺錫四族半導體材料之磊晶材料成長、應力隨鍺錫磊晶成長厚度之分析、及熱穩定性之研究。鍺錫材料其電洞遷移率高於鍺材料，使之有很大的潛力做為電晶體p 型通道之候選人。且於鍺材料中摻雜約8%的錫可以使其有機會變成直接能隙材料，因此鍺錫材料目前已被廣泛用來當作發光元件及光偵測器之材料首選。在本論文中，我們利用二鍺烷及四氯化錫做為化學氣象沉積氣體先驅物於鍺緩衝層上進行磊晶，並搭配低溫成長來成長出鍺錫磊晶層。磊晶厚度低於磊晶臨界厚度具有壓縮應變之薄鍺錫磊晶層，以及磊晶厚度高於磊晶臨界厚度具有鬆弛應變之厚鍺錫磊晶層，均於此論文中製備及探討。此外，具有不同摻雜載子型態之鍺錫磊晶層之材料分析及熱穩定性亦在此部分被研究。在相同的錫濃度之鍺錫材料中，具有不同型態之摻雜載子，其熱穩定性會有所不同，其原因有可能是因為雜質互相擴散常數的差異或載子半徑大小所導致。當鍺錫材料環境不處於熱穩定條件下，會導致錫擴散或析出現象，會大幅的影響鍺錫材料的濃度分布及形貌，若是應用於電晶體元件中，將會導致元件短路問題。因此，透過熱穩定性研究，可以將結果應用在後續鍺錫材料元件製備過程中，避免錫析出或擴散之溫度參考。 本論文的第三個部分為鍺錫接面二極體之製備與特性分析。透過離子佈植的方法並搭配不同的後續熱製程來活化，例如快速熱退火或微波熱退火方法。高錫濃度([Sn]=15%)及高鬆弛應變(Relaxation=80%)之鍺錫磊晶層被選用做為研究，未來可應用於鍺錫n 型通道金氧半場效電晶體之源極和汲極。 本論文之最後部分將探討垂直堆疊鍺矽n 型閘極環繞式電晶體之光響應特性。於垂直堆疊閘極環繞式電晶體之製程中，透過不同的蝕刻時間及蝕刻Fin的寬度優化，可以成功的蝕刻出三種不同元件，用以做為光響應特性分析比較。分別為(1)鍺矽垂直堆疊通道與鍺寄生通道並存之元件、(2)鍺矽垂直堆疊通道之元件、(3)鍺寄生通道之元件。透過紅外光照射於通道上，所量測到的光響應現象會有所不同。具有鍺矽垂直堆疊通道的元件會量測到閾值電壓的位移，而具有鍺寄生通道之元件會觀察到光電流的產生。在鍺矽垂直堆疊通道與鍺寄生通道並存的元件可同時觀察到閾值電壓位移及光電流產生。詳細的原因將透過能帶圖於本論文中闡述。寄生通道由於具有相當大的缺陷密度，因此光激發載子可透過缺陷而流動，產生光電流。寄生通道的存在會導致電晶體的電性表現降低，可透過紅外光檢測的方法，可以以非破壞性且快速的方法來檢視垂直堆疊閘極環繞式電晶體蝕刻過程中，寄生通道是否存在。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T09:26:20Z (GMT). No. of bitstreams: 1 U0001-1012202122574200.pdf: 8040136 bytes, checksum: 916a266613fd91411e44ae598273804e (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | Table of Content Related Publication (相關論文發表) ..... I 誌謝 ..... IV 摘要 ..... V Abstract ..... VIII Table of Content ..... XII List of Figures ..... XIV List of Tables ..... XIX Chapter 1 Introduction ..... 1 1.1 Motivation ..... 1 1.1.1 The Invention of Transistor and More Moore Scaling ..... 1 1.1.2 High Mobility Ge-based Channel Materials ..... 4 1.2 Dissertation Organization ..... 6 Chapter 2 Selective epitaxial growth of Ge ..... 16 2.1 Introduction ..... 16 2.1.1 Benefits of Ge-based Optical Materials ..... 16 2.1.2 Methods for defect reduction ..... 17 2.1.3 Application of selective epitaxial growth ..... 18 2.2 Growth and characterization ..... 19 2.3 Summary ..... 23 Chapter 3 Epitaxial Growth of Strained and Relaxed GeSn Epilayers Using Ge2H6 and SnCl4 ..... 31 3.1 Introduction ..... 31 3.2 Growth and characterization ..... 33 3.2.1 Mechanism of CVD grown-GeSn ..... 33 3.2.2 Growth rate and Sn content Enhancement by SnCl4 precursor ..... 35 3.2.3 The thermal equilibrium critical thickness and metastable critical thickness vs. Sn fraction ..... 36 3.2.4 Epitaxy of Strained GeSn and Relaxed GeSn ..... 38 3.2.5 Sn segregation ..... 49 3.3 Summary ..... 52 Chapter 4 Material and Thermal Stability Characteristics of CVD-grown GeSn Layers ..... 83 4.1 Introduction ..... 83 4.2 Growth and characterization ..... 84 4.2.1 Thermal stability of CVD-Grown GeSn with strain dependence ..... 84 4.2.2 Thermal stability of CVD-Grown GeSn with doping dependence ..... 86 4.3 Summary ..... 89 Chapter 5 GeSn n+/p Diodes by Ion Implantation and Microwave Annealing ..... 96 5.1 Introduction ..... 96 5.2 CVD Epitaxy and Material Characterization ..... 96 5.3 Fabrication process for GeSn n+/p Diodes ..... 97 5.4 Electrical Charactrizations for GeSn n+/p Diodes ..... 98 5.5 Summary ..... 99 Chapter 6 Optical Detection by Infrared Response from Parasitic Channels and Vertically Stacked GeSi nGAAFETs ..... 106 6.1 Introduction ..... 106 6.2 CVD Epitaxy and Material Characterization ..... 107 6.3 Fabrication of Vertically Stacked GeSi Gate-all-around nFETs ..... 108 6.4 Charactrization of GeSi nGAAFETs with Infrared Respense ..... 111 6.5 Summary ..... 115 Chapter 7 Summary and Future Work ..... 131 7.1 Summary ..... 131 7.2 Future Work ..... 134 Reference ..... 136 | |
| dc.language.iso | en | |
| dc.subject | 選擇性磊晶成長 | zh_TW |
| dc.subject | 化學氣相沉積 | zh_TW |
| dc.subject | 鍺錫 | zh_TW |
| dc.subject | 鍺矽 | zh_TW |
| dc.subject | 鍺 | zh_TW |
| dc.subject | 垂直堆疊通道 | zh_TW |
| dc.subject | 寄生通道 | zh_TW |
| dc.subject | 源汲極製備 | zh_TW |
| dc.subject | 紅外光響應 | zh_TW |
| dc.subject | 鍺錫接面二極體 | zh_TW |
| dc.subject | 微波退火 | zh_TW |
| dc.subject | 臨界厚度 | zh_TW |
| dc.subject | 熱穩定 | zh_TW |
| dc.subject | 閘極環繞式電晶體 | zh_TW |
| dc.subject | 錫析出 | zh_TW |
| dc.subject | 交互擴散 | zh_TW |
| dc.subject | critical thickness | en |
| dc.subject | Ge | en |
| dc.subject | GeSi | en |
| dc.subject | GeSn | en |
| dc.subject | RTCVD | en |
| dc.subject | selective epitaxial growth | en |
| dc.subject | interdiffusion | en |
| dc.subject | Sn segregation | en |
| dc.subject | thermal stability | en |
| dc.subject | microwave annealing | en |
| dc.subject | GeSn diode | en |
| dc.subject | Epi structure design | en |
| dc.subject | GAAFETs | en |
| dc.subject | Stacked channels | en |
| dc.subject | Nanosheet | en |
| dc.subject | parasitic channel | en |
| dc.subject | photoresponse | en |
| dc.subject | infrared response | en |
| dc.title | 鍺/鍺錫化學氣相磊晶異質成長與n型場效電晶體接面製備與特性分析 | zh_TW |
| dc.title | Heteroepitaxy Ge/GeSn by Chemical Vapor Deposition with Fabrication and Characterization of Junction for nMOSFETs | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.author-orcid | 0000-0003-1801-768X | |
| dc.contributor.oralexamcommittee | 李敏鴻(Hsin-Tsai Liu),林中一(Chih-Yang Tseng),林吉聰,林楚軒,張書通,彭成毅 | |
| dc.subject.keyword | 鍺,鍺矽,鍺錫,化學氣相沉積,選擇性磊晶成長,交互擴散,錫析出,熱穩定,臨界厚度,微波退火,鍺錫接面二極體,源汲極製備,閘極環繞式電晶體,垂直堆疊通道,寄生通道,紅外光響應, | zh_TW |
| dc.subject.keyword | Ge,GeSi,GeSn,RTCVD,selective epitaxial growth,interdiffusion,Sn segregation,thermal stability,critical thickness,microwave annealing,GeSn diode,Epi structure design,GAAFETs,Stacked channels,Nanosheet,parasitic channel,photoresponse,infrared response, | en |
| dc.relation.page | 149 | |
| dc.identifier.doi | 10.6342/NTU202104529 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2021-12-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| U0001-1012202122574200.pdf 未授權公開取用 | 7.85 MB | Adobe PDF |
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