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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81635完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Hsin-Yi Peng | en |
| dc.contributor.author | 彭馨儀 | zh_TW |
| dc.date.accessioned | 2022-11-24T09:25:01Z | - |
| dc.date.available | 2022-11-24T09:25:01Z | - |
| dc.date.copyright | 2022-02-16 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-02-09 | |
| dc.identifier.citation | [1] I. M. Yi, et al., “A time-based receiver with 2-tap decision feedback equalizer for single-ended mobile DRAM interface,” IEEE J. Solid-State Circuits, vol. 53, no. 1, pp.1-10, Jan. 2018. [2] P.W. Chiu, S. Kundu, and Q. Tang, “A 65-nm 10-Gb/s 10-mm on-chip serial link featuring a digital-intensive time-based decision feedback equalizer,” IEEE J. Solid-State Circuits, vol. 53, no. 4, pp.1203-1212, Apr. 2018. [3] P.W. Chiu and C. Kim, 'A 32Gb/s digital-intensive single-ended PAM-4 transceiver for high-speed memory interfaces featuring a 2-tap time-based decision feedback equalizer and an in-situ channel-loss monitor,' IEEE Int. Solid- State Circuits Conf. (ISSCC), 2020, pp. 336-338. [4] A. Ramachandran, A. Natarajan and T. Anand, 'A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: integrated pulse width modulation (iPWM) in 65nm CMOS,' IEEE Int. Solid-State Circuits Conf. (ISSCC), 2017, pp. 488-489. [5] H. J. Chi, and J. S. Lee, “A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2053-2063, Sep. 2011. [6] Z. Hong, Y. Liu and W. Chen, 'A 3.12 pJ/bit, 19–27 Gbps receiver with 2-tap DFE embedded clock and data recovery,' IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2625-2634, Nov. 2015. [7] J. Lee, K. Lee, H. Kim, B. Kim, K. Park and D. Jeong, 'A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference,' IEEE J. Solid-State Circuits, vol. 55, no. 8, pp. 2186-2195, Aug. 2020. [8] P. Osheroff, G. S. L. Rue, and S. Gupta, “A highly linear 4 GS/s uncalibrated voltage-to-time converter with wide input range,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 89–92, May 2016. [9] T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, “A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1298–1305, Apr. 2009. [10] M. H. Nazari and A. Emami-Neyestanak , “A 15-Gb/s 0.5-mW/Gbps two-tap DFE receiver with far-end crosstalk cancellation,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2420–2432, Oct. 2012. [11] T. Musah et al., “A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 3079–3090, Dec. 2014. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/81635 | - |
| dc.description.abstract | 現今，傳輸通道的有限頻寬導致傳輸訊號失真，使位元錯誤率升高，為了解決此問題，等化器被廣泛的使用，但隨著製程的進步，電源電壓逐漸下降，等化器的運算電路在設計上變得更困難，因此，將使用時域架構來避免此狀況。此外，通道衰減的特性會隨通道材質及長度的不同而改變，因此，自動調整係數對於等化器是有需求的。 本論文提出一個有時間偏差校正功能之10.5Gbps可適性2-tap時域決策回授等化器，實作於40奈米製程中，採用SSLMS演算法來實現可適性，根據量測結果:時域決策回授等化器可適當的補償小於14.5dB衰減的串列資料，其中，等化器的面積為126um × 110um，等化器的功率為10.3mW。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T09:25:01Z (GMT). No. of bitstreams: 1 U0001-0802202210140500.pdf: 3878151 bytes, checksum: 53f149d902421d7b5a13b372f2e61d58 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 摘要 I 目錄表 III 圖示列表 IV 表格列表 VI 第一章 引言 1 1.1 概論 2 1.2 有線通訊系統 2 1.3 等化器 3 1.3.1 連續時間線性等化器 3 1.3.2 判決回授等化器 3 1.4 論文組織 4 第二章 2-tap時域決策回授等化器及時間偏差校準電路及SSLMS演算法 5 2.1 研究動機 6 2.2 電路架構 7 2.2.1 差動2-tap時域決策回授等化器 7 2.2.2 時域決策回授等化器之時間限制與規格 10 2.2.3 主要電路描述 12 2.3 子電路描述 13 2.3.1 電壓時間轉換器 13 2.3.2 數位時間轉換器 15 2.3.3 時間比較器 16 2.3.4 TB-DFE模擬 17 2.3.5 偏差校正電路 18 2.3.6 SSLMS演算法 19 2.4 佈局與量測結果 23 2.4.1 量測環境與晶片佈局 23 2.4.2 量測結果 24 第三章 結論及未來改善 29 3.1 結論 30 3.2 未來改善 30 參考文獻 31 | |
| dc.language.iso | zh-TW | |
| dc.subject | 時間偏差校正 | zh_TW |
| dc.subject | 時域 | zh_TW |
| dc.subject | 適應性演算法 | zh_TW |
| dc.subject | 決策回授等化器 | zh_TW |
| dc.subject | 高速接收器 | zh_TW |
| dc.subject | time-based | en |
| dc.subject | offset calibration | en |
| dc.subject | high speed transceiver | en |
| dc.subject | decision feedback equalizer | en |
| dc.subject | adaptive | en |
| dc.title | 一個10.5Gbps可適性時域決策回授等化器 | zh_TW |
| dc.title | A 10.5Gbps Adaptive Time-Based Decision Feedback Equalizer | en |
| dc.date.schoolyear | 110-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Yu-Liang Yang),林宗賢(Hsin-Hung Yeh) | |
| dc.subject.keyword | 時域,適應性演算法,決策回授等化器,高速接收器,時間偏差校正, | zh_TW |
| dc.subject.keyword | time-based,adaptive,decision feedback equalizer,high speed transceiver,offset calibration, | en |
| dc.relation.page | 32 | |
| dc.identifier.doi | 10.6342/NTU202200363 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2022-02-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-0802202210140500.pdf 未授權公開取用 | 3.79 MB | Adobe PDF |
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