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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 廖世偉(Shih-wei Liao) | |
| dc.contributor.author | Hsien-An Wu | en |
| dc.contributor.author | 吳弦安 | zh_TW |
| dc.date.accessioned | 2022-11-24T03:05:44Z | - |
| dc.date.available | 2021-11-03 | |
| dc.date.available | 2022-11-24T03:05:44Z | - |
| dc.date.copyright | 2021-11-03 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-10-21 | |
| dc.identifier.citation | [1] Bingfeng Mei, Serge Vernalde, Diederik Verkest, and Hugo De ManRudy Lauwereins. Adres: An architecture with tightly coupled vliw processor and coarsegrained reconfigurable matrix. In International Conference on Field Programmable Logic and Applications, 2003. [2] Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, and Charles R. Moore. Exploiting ilp, tlp, and dlp with the polymorphous trips architecture. In Bingfeng Mei and Serge Vernalde and Diederik Verkest and Hugo De ManRudy Lauwereins, 2003. [3] V. Govindaraju, C. Ho, T. Nowatzki, J. Chhugani, N. Satish, K. Sankaralingam, and C. Kim. Dyser: Unifying functionality and parallelism specialization for energyefficient computing. IEEE Micro, 32(5):38–51, 2012. [4] Artur Podobas, Kentaro Sano, and Satoshi Matsuoka. A survey on coarsegrained reconfigurable architectures from a performance perspective. IEEE Access, 2020. [5] Sukjin Kim, YoungHwan Park, Jaehyun Kim, Minsoo Kim, Wonchang Lee, and Shihwa Lee. Flexible video processing platform for 8k uhd tv. In IEEE Hot Chips 27 Symposium (HCS), 2015. [6] Z. Zhao, W. Sheng, Q. Wang, W. Yin, P. Ye, J. Li, and Z. Mao. Towards higher performance and robust compilation for cgra modulo scheduling. IEEE Transactions on Parallel and Distributed Systems, 31(9):2201–2219, 2020. [7] Bjorn De Sutter, Praveen Raghavan, and Andy Lambrechts. Coarsegrained reconfigurable array architectures. In Shuvra S. Bhattacharyya, editor, Handbook of signal processing systems, pages 427–472. Springer, 2019. [8] Shail Dave. CCF manual, 2019. [9] B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. Exploiting looplevel parallelism on coarsegrained reconfigurable architectures using modulo scheduling. IEE Proceedings Computers and Digital Techniques, 150(5):255–, 2003. [10] B. Ramakrishna Rau. Iterative modulo scheduling: An algorithm for software pipelining loops. In Proceedings of the 27th Annual International Symposium on Microarchitecture, MICRO 27, page 63–74, New York, NY, USA, 1994. Association for Computing Machinery. [11] Bingfeng Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. Dresc: a retargetable compiler for coarsegrained reconfigurable architectures. In 2002 IEEE International Conference on FieldProgrammable Technology, 2002. (FPT). Proceedings., pages 166–173, 2002. [12] M. Hamzeh, A. Shrivastava, and S. Vrudhula. Epimap: Using epimorphism to map applications on cgras. In DAC Design Automation Conference 2012, pages 12801287, 2012. [13] M. Hamzeh, A. Shrivastava, and S. Vrudhula. Regimap: Registeraware applica40 doi:10.6342/NTU202100729 tion mapping on coarsegrained reconfigurable architectures (cgras). In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–10, 2013. [14] S. Yin, X. Yao, D. Liu, L. Liu, and S. Wei. Memoryaware loop mapping on coarsegrained reconfigurable architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(5):1895–1908, 2016. [15] S. Dave, M. Balasubramanian, and A. Shrivastava. Ramp: Resourceaware mapping for cgras. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pages 1–6, 2018. [16] Davis Blalock, Jose Javier Gonzalez Ortiz, Jonathan Frankle, and John Guttag. What is the state of neural network pruning?, 2020. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/80394 | - |
| dc.description.abstract | Edge AI在現在的社會越來越重要，尤其是在移動端關於reference的應用，目前主流的架構如GPU、CPU、ASIC無法很好的滿足Edge AI的特性，也就是在有限的能源消耗下，並且達到一定的運算力，所以現在逐漸在其他的架構上做探索，對於CGRA(Coarse-Grained Reconfigurable Architectures)的探索也在這幾年來逐漸上升，CGRA很好的在能耗上跟運算彈性上做出取捨，不過其編譯的複雜度也很大的阻礙了CGRA的發展; CGRA的編譯是一個三維的配對問題，分別是時間和空間，目前時間上的順序主要是靠modulo scheduling 來生成 software pipelining 後的執行順序。 而空間上的配對則是要把分配到同個時間執行的指令，依照相對關係分配到2D的CGRA上。在本論文中我們主要針對空間分配的部分，我們觀察目前編譯的演算法在實際空間配對時會遇到的問題，並把問題做出分類跟觀察其特性，使問題可以提早被發現。我們的改進，可以在不影響編譯後程式的效能的前提下，大幅縮短編譯的時間，和一定程度上的改進程式的效能。我們的方法可以在目前的演算法的基礎下，改進程式5.9%的效能和9.6倍的編譯時間。同時，在Edge AI模型中最常用到的convolution運算中，我們針對已經經過權重剪枝的模型，提出了一個方法能同時大幅度的改進編譯結果跟速度，結果取決於剪枝的程度，通常我們能數倍的改善效能和編譯時間。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2022-11-24T03:05:44Z (GMT). No. of bitstreams: 1 U0001-1702202123433300.pdf: 968790 bytes, checksum: 71fb3c977701968cf47b1deaf5b9d0a6 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | Acknowledgements 3 摘要 5 Abstract 7 Contents 9 Chapter 1 INTRODUCTION 1 Chapter 2 BACKGROUND 5 2.1 CGRA Architecture 5 2.2 CGRA Compilation 7 2.2.1 Integrated Mapping 9 2.2.2 Decomposed Mapping 10 2.2.2.1 Schedule First then Integrate Placement and Routing 10 2.2.2.2 Integrate Schedule and Routing then do Placement 12 Chapter 3 MOTIVATION 13 3.1 Survey and Observation 13 3.1.1 Observation in the RobustMap 13 3.2 Influence of our Observation 14 4.1 RobustMap 17 4.1.1 Temporal Mapping 17 4.1.2 Spatial Mapping 19 4.2 PruneMap 20 4.2.1 Why Based On RobustMap 20 4.2.2 Ours Method 20 Chapter 5 CONVOLUTION OPTIMIZATION 25 5.1 Why Software Pipelining 25 5.2 Background of Convolution Optimization 26 5.3 Convolution Compilation 27 Chapter 6 EXPERIMENT AND DISCUSSION 29 6.1 Environment 29 6.2 General Purpose Mapping 30 6.2.1 Performance 30 6.2.2 Compilation Time 31 6.3 Convolution Mapping 32 Chapter 7 CONCLUSION 35 References 39 | |
| dc.language.iso | en | |
| dc.subject | CGRA 編譯 | zh_TW |
| dc.subject | CGRA | zh_TW |
| dc.subject | 可重組運算 | zh_TW |
| dc.subject | CGRA | en |
| dc.subject | reconfigurable computation | en |
| dc.subject | CGRA compilation | en |
| dc.title | CGRA 的編譯優化 | zh_TW |
| dc.title | Improving Compilation for CGRA | en |
| dc.date.schoolyear | 109-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 徐慰中(Hsin-Tsai Liu),黃敬群(Chih-Yang Tseng),洪士灝,施吉昇 | |
| dc.subject.keyword | CGRA,可重組運算,CGRA 編譯, | zh_TW |
| dc.subject.keyword | CGRA,reconfigurable computation,CGRA compilation, | en |
| dc.relation.page | 41 | |
| dc.identifier.doi | 10.6342/NTU202100729 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2021-10-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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