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標題: | 可撓性垂直堆疊式互補式氧化物薄膜電晶體反相器電路之研究 Flexible Vertically-Stacked Complementary Inverter with Oxide Thin-Film Transistors |
作者: | Wei-Chen Lin 林韋丞 |
指導教授: | 陳奕君(I-Chun Cheng) |
關鍵字: | 可撓性電子元件,薄膜電晶體,垂直堆疊式CMOS反相器,氧化亞錫,氧化鋅,閘極偏壓穩定性,照光穩定性, flexible electronics,thin-film transistor,vertically-stacked complementary inverter,tin monoxide,zinc oxide,bending test,gate-bias stress stability,light illumination stress stability, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 本研究以相對低溫之製程條件,成功將垂直堆疊結構的互補式反相器製作於可撓性塑膠基板上。該互補式反相器電路由p型及n型薄膜電晶體組成,兩者之通道層材料皆屬金屬氧化物半導體,p型材料為氧化亞錫,n型材料為氧化鋅。製程為優先製作上閘極p型薄膜電晶體,接著垂直堆疊下閘極n型薄膜電晶體在p型電晶體上方。兩者共用閘極,並利用垂直通孔與互連導線形成垂直堆疊式互補式氧化物薄膜電晶體反相器。研究過程分別對p型與n型薄膜電晶體進行優化,以尋求元件之最佳表現。
在垂直式CMOS反相器之p型及n型薄膜電晶體表現中,通道W/L皆設計為40 μm / 20 μm,於| VDS | = 1 V下,p型之場效載子遷移率、電流開關比、次臨界擺幅、臨界電壓分別為0.68 cm2/V-s、104、1.54 V/dec、4.8 V;而n型分別為0.58 cm2/V-s、107、0.31 V/dec、3.3 V。在CMOS反相器表現中,當電源供應VDD為10 V時,電壓增益達36 V/V,雜訊邊界NMH及NML分別為3.9及5.0 V,其具高增益及平衡之雜訊邊界,而在彎曲測試中,CMOS反相器之各項特徵參數皆無明顯之變化。 研究最後探討可撓性垂直堆疊式CMOS反相器下層之上閘極p型氧化亞錫薄膜電晶體之穩定性。在閘極偏壓穩定性測試中,臨界電壓偏移符合延展式指數關係式,推測此不穩定性主要來自介電層與通道層界面之電荷捕獲,或是介電層本身之電荷捕獲,且當元件受彎曲時,此偏壓不穩定性將更趨嚴重,其中又以壓應變情況下較為顯著。而在照光穩定性測試中,照光下的電晶體之開電流及關電流皆略微上升、臨界電壓朝正方向偏移,推測其主要為光電導效應所導致。而同時施以照光及閘極偏壓時,正偏壓下,臨界電壓向正方向偏移(約2.2 V),推測其機制主要為介電層與通道層界面或是介電層本身之電荷捕獲。而負偏壓下,臨界電壓同樣向正方向偏移(約1.3 V),推測其原因為照光下引發SnO薄膜內部產生過多之自由電子,受負偏壓排斥注入緩衝層二氧化鉿中形成陷井電荷。 In this research, a vertically-stacked flexible complementary inverter composed of a bottom-gate n-type zinc oxide (ZnO) thin-film transistor (TFT) and a top-gate p-type tin monoxide (SnO) TFT processed at low substrate temperatures was demonstrated. The channel layer material of the two types of transistors was oxide semiconductors. In terms of process, the top-gate p-type thin-film transistor was first fabricated, which was then vertically stacked below the bottom-gate n-type thin-film transistor, with the common gate shared by the two types of TFTs, where vertical through holes and interconnect wires were used to form a vertically-stacked complementary oxide-TFT based inverter. In this study, the p-type and n-type TFTs were optimized to find the best performance. The W/L of the both p-type and n-type TFT channels were designed to be 40 μm / 20 μm. In terms of performance of the p-type and n-type TFTs of the vertically stacked CMOS inverter, at | VDS | = 1 V, the field-effect carrier mobility, on/off current ratio, sub-threshold swing, and threshold voltage of the p-type transistor were 0.68 cm2/V-s, 104, 1.54 V/decade and 4.8 V, respectively, while those of the n-type transistor were 0.58 cm2/V-s、107、0.31 V/decade、3.3 V, respectively. In light of performance of the CMOS inverter, at a supply voltage (VDD ) of 10 V, the voltage gain reached 36 V/V, and the noise margins became balanced, with the noise margin high (NMH) and noise margin low (NML) being 3.9 V and 5.0V, respectively. In the bending test, the characteristic parameters of the CMOS inverter showed no obvious changes. Finally, this study investigated the stability of the top-gate p-type SnO TFT. In the gate-bias stability test, the threshold voltage offset was in accordance with the stretched-exponential time dependence equation, based on which the instability was speculated to mainly originate from charge trapping at the interface or the gate dielectric. Moreover, when the SnO TFT was bent, the bias instability increased, which was more significant for the compression strain case. Under light illumination, both the on-current and off-current of the transistors increased slightly, with the threshold voltage shifting toward the positive direction, which was speculated to mainly originate from photoconductive effects. Under light illumination, the threshold voltage shifted toward the positive direction by 2.2 V if a positive gate-bias was applied, which was speculated to mainly originate from charge trapping at the interface or the gate dielectric, while the threshold voltage shifted toward the positive direction by 1.3 V if a negative gate-bias was applied, which was speculated to originate from the fact that, under light illumination, excessive free electrons generated in the SnO film were driven by the negative bias into the hafnium oxide buffer layer to form trapped charges. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78948 |
DOI: | 10.6342/NTU201803708 |
全文授權: | 有償授權 |
顯示於系所單位: | 光電工程學研究所 |
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