如何用頁面重寫降低快閃記憶體中錯誤更正碼的成本

Abstract

近年來，快閃記憶體的儲存密度逐漸上升。新興的高密度裝置，像是多級單元或三級單元的可靠度比較低，所以需要較強的錯誤更正碼以承受更多的寫入/抹除次數。然而較強的錯誤更正碼需要額外空間及效能的管理費用，且他需要昂貴的硬體支援。若裝置可以在固定的寫入/抹除次數中承受更多次的寫入的話，裝置的寫入/抹除次數以及錯誤更正碼成本的需求就可以被減緩。在此篇論文中，我們提出了一個考慮干擾的頁面重寫機制並使用他來儲存熱數據，使裝置在固定寫入/抹除次數下可以承受更多次的寫入。我們將會藉由一系列的實驗驗證此機制的能力。最後結果顯現出藉由我們提出的機制，我們可以讓裝置不犧牲耐久度的情況下減少寫入/抹除次數以及錯誤更正碼的需求成本。

The density of NAND flash device continues to increase in recent years. Emerging high density devices like MLC or TLC has lower reliability and requires stronger ECC to tolerate more number of P/E cycle. However, strong ECC brings space and performance overhead, and it requires costly hardware support. If the device can tolerate more number of writes within fixed P/E cycle, the P/E cycle and ECC requirement can be relaxed. In this work, we propose a disturbance-aware page rewriting and use it to store write-hot data so that the number of write operations a device can tolerated within fixed P/E cycle can be improved. The capability of the proposed design is evaluated by a series of experiments, and the results show that with our proposed design, the P/E cycle as well as the ECC requirement can be reduced without sacrificing its endurance.