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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 楊家驤 | |
| dc.contributor.author | Yi-Cheng Lin | en |
| dc.contributor.author | 林邑政 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:56:39Z | - |
| dc.date.available | 2025-02-24 | |
| dc.date.copyright | 2020-02-24 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-02-18 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78431 | - |
| dc.description.abstract | 語音辨識是將語音訊號轉換成文字的技術，目前已廣泛應用於可攜式裝置、智慧家庭、機器人、自動駕駛等。為了達到更好的辨識度，語音辨識系統可採用雙向遞迴神經網路，但需要大量的資料計算與儲存。傳統的雙向遞迴神經網路通常使用長短期記憶模型，本論文採用輕量門控遞迴單元作為其運算核心，可以在維持準確率的同時，有效地減少模型的參數量與運算複雜度。然而，執行語音辨識時，雙向遞迴神經網路仍耗費大多數的運算時間，因此本研究整合數種神經網路壓縮技術，包含比例係數剪枝、多位元叢聚與線性量化，以大幅地降低神經網路模型大小及所需運算量。其中比例係數剪枝將擁有較小比例係數的神經元及所有對應權重進行剪枝，可降低88%的記憶體與運算量。多位元叢聚將權重分類成數個群體，並在儲存時使用索引指數標記，進一步降低84%的權重記憶體。線性量化減少輸入與權重的位元數，可降低91%的運算量。最終該神經網路壓縮技術可以在只降低1%的準確率下減少98%的模型大小，僅需593KB的儲存空間即可在TIMIT語料庫上達到15.3%的音素錯誤率。本論文所提出之加速器硬體架構以可程式化邏輯陣列進行驗證，和文獻上最佳設計相比，達到3.5-8.2倍的吞吐量，而在只輸入單一筆語音訊號的情形下，每秒運算幀數達到2.4-16.5倍，並具有最低的音素錯誤率。 | zh_TW |
| dc.description.abstract | Speech recognition is a technique that converts speech signals to texts. It has been extensively used for a variety of applications, including wearable devices, home automation, robots, and self-driving cars. To enhance the accuracy, bidirectional recurrent neural networks (BRNN) are adopted for speech recognition. This introduces an immense amount of computational complexity and a huge model size. In contrast to the conventional long short-term memory (LSTM), light gated recurrent unit (Light GRU) is adopted in this work to achieve a high accuracy but with fewer parameters. Since the BRNN dominates the execution time for speech recognition, this work presents a network compression scheme that consists of scaling factor pruning (SFP), multi-bit clustering (MBC), and linear quantization (LQ). SFP prunes the neurons based on trainable scaling factors, and compress both the model size and computational complexity by 88%. MBC classifies weights into groups using indices to further compress the model size by 84%. LQ decreases the bitwidth of inputs and weights, and further reduces the computational complexity by 91%. Based on the proposed network compression scheme, the model size is reduced by 98%, with only a 1% drop in accuracy. The phone error rate for the TIMIT corpus remains at 15.3% with a model size of merely 593 KB. Compared to current state-of-the-art designs, the presented BRNN FPGA (Field-Programmable Gate Array) accelerator achieves a 3.5-to-8.2x higher throughput and a 2.4-to-16.5x higher frame rate at a batch size of one, despite the lowest phone error rate. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:56:39Z (GMT). No. of bitstreams: 1 ntu-109-R06943023-1.pdf: 6615229 bytes, checksum: 87c424eef02bcfc199f8e33e3444ae05 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 ii
誌謝 iii 摘要 iv ABSTRACT v Contents vii List of Figures ix List of Tables x 1 INTRODUCTION 1 2 PRELIMINARIES 5 2.1 Speech Recognition System 5 2.2 Feature Extraction 5 2.3 RNN Model 6 2.3.1 Light GRU 7 2.3.2 Weight-sharing Bidirectional RNNs 9 2.3.3 RNN Model in Speech Recognition 9 2.4 Linguistic Search Algorithm 11 3 NETWORK COMPRESSION 14 3.1 Scaling Factor Pruning 15 3.1.1 Structured Pruning 15 3.1.2 Network Slimming 15 3.1.3 Improvement and Implementation 16 3.1.4 Experimental Result 18 3.2 Multi-bit Clustering 19 3.2.1 Algorithm 19 3.2.2 Improvement and Implementation 21 3.2.3 Experimental Result 22 3.3 Linear Quantization 22 3.4 Effect of Network Compression Scheme 24 4 BRNN HARDWARE ACCELERATOR 26 4.1 Overall Architecture 26 4.2 On-chip Memory 27 4.3 LiGRU Engine 28 4.4 Hidden State Buffer 30 4.5 Computation Flow 31 5 EXPERIMENTAL VERIFICATION 33 5.1 System Setup 33 5.2 Performance Evaluation 34 5.3 Hardware Implementation 34 5.4 Design Comparison 36 6 CONCLUSION 38 References 39 | |
| dc.language.iso | en | |
| dc.subject | 可程式化邏輯陣列實現 | zh_TW |
| dc.subject | 語音辨識 | zh_TW |
| dc.subject | 遞迴神經網路 | zh_TW |
| dc.subject | 雙向遞迴神經網路 | zh_TW |
| dc.subject | 輕量門控遞迴單元 | zh_TW |
| dc.subject | 神經網路壓縮 | zh_TW |
| dc.subject | FPGA implementation | en |
| dc.subject | speech recognition | en |
| dc.subject | recurrent neural network (RNN) | en |
| dc.subject | bidirectional RNN (BRNN) | en |
| dc.subject | light GRU | en |
| dc.subject | network compression | en |
| dc.title | 應用於語音辨識之雙向遞迴神經網路硬體加速器設計與實現 | zh_TW |
| dc.title | Design and Implementation of a Bidirectional RNN FPGA Accelerator for Speech Recognition | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 簡韶逸,劉宗德,闕河鳴 | |
| dc.subject.keyword | 語音辨識,遞迴神經網路,雙向遞迴神經網路,輕量門控遞迴單元,神經網路壓縮,可程式化邏輯陣列實現, | zh_TW |
| dc.subject.keyword | speech recognition,recurrent neural network (RNN),bidirectional RNN (BRNN),light GRU,network compression,FPGA implementation, | en |
| dc.relation.page | 43 | |
| dc.identifier.doi | 10.6342/NTU202000421 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-02-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2025-02-24 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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