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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78317完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪銘輝(Minghwei Hong) | |
| dc.contributor.author | Yen-Hsun Lin | en |
| dc.contributor.author | 林延勳 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:50:55Z | - |
| dc.date.available | 2025-08-06 | |
| dc.date.copyright | 2020-08-11 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-06 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78317 | - |
| dc.description.abstract | 三五族砷化銦鎵半導體因其高電子遷移率被廣泛運用於高速元件與許多凝態物理研究中。近年來，高效能砷化銦鎵金氧半場效能電晶體被提出可運用於邏輯元件、高速射頻應用與進一步量子運算元件架構中，其實現關鍵在於高品質低缺陷密度的高介電氧化物/砷化銦鎵半導體的異質結構。然而，目前的瓶頸在於多數高介電氧化物/砷化銦鎵半導體異質結構仍有高介面態位密度(Dit)、高邊界缺陷密度(Nbt)與低熱穩定性問題。
本篇論文中，透過臨場原子層沉積或分子束磊晶沉積氧化釔在不同銦比例的砷化銦鎵上(GaAs, In0.2Ga0.8As, In0.53Ga0.47As)，我們製備出高品質高介電氧化物/三五族半導體異質結構有效解決上述面臨的瓶頸。首先，我們發現臨場成長的原子層沉積氧化釔是以單晶型態成長在潔淨的砷化鎵(001)表面上。這是首次利用原子層沉積的方式在(001)面的半導體上成長出單晶氧化物。透過同步輻射X光繞射研究，僅2.3奈米厚度的氧化釔薄膜即具有優異的結晶度。原子層沉積氧化釔/砷化鎵的異質結構具有承受900oC 60s退火的高溫熱穩定性，並展現出1-2x1012 cm-2eV-1的介面態位密度分布且沒有能帶中央的介面態位峰。當我們進一步將原子層沉積氧化釔進行超高真空熱退火，其電性特性(例：電容電壓特性中的聚積區頻率分散度)與介面態位密度都獲得進一步改善。尤其介面態位密度下降到2-6x1011 cm-2eV-1 是目前由原子層沉積成長的氧化物/砷化鎵(001)異質結構中最低紀錄。 我們另透過分子束磊晶成長氧化釔的方式，在砷化鎵與20%砷化銦鎵(In0.2Ga0.8As)上也得到優異的電性特性。在p型與n型砷化(銦)鎵上都呈現對稱的電容電壓曲線且聚積區頻率分散度均低於2%/dec，顯示該結構中的介面態位密度和邊界缺陷密度都非常低。透過電導量測擷取出的介面態位密度在砷化鎵和砷化銦鎵上都達到1-3x1011 cm-2eV-1，是目前最低紀錄水準。 除了低銦含量的砷化銦鎵外，我們在高銦比例的砷化銦鎵上也有所突破。過去在53%砷化銦鎵中，近價帶區域的介面態位密度經常是高達1012-1013 cm-2eV-1 顯示高銦比例的砷化銦鎵表面並沒有被妥善鈍化。我們利用臨場成長氧化釔在p型53%砷化銦鎵上，在以下數個方面都突破過去的成果。氧化釔/砷化銦鎵異質結構能承受800oC的熱退火，顯示其介面優異的熱穩定性。電容電壓特性中聚積區頻率分散度，在室溫和77K的量測下也分別達到5% 和1%。這樣優異的電容電壓特性幾乎無頻率分散度的表現是過去在p型砷化銦鎵上從未報導過的，也顯示我們氧化釔/砷化銦鎵異質結構中具有非常低的介面態位密度與邊界缺陷密度。基於這些優異的電容電壓特性，我們在介面態位密度的擷取上也進行了變溫電導量測與相關討論。擷取出的介面態位密度從價帶邊緣到能帶中央處達到3-7x1011 cm-2eV-1 的水準，比過去報導的成果低了1-2個數量級。 以上成果在高介電氧化物/三五族半導體異質結構的研究中分別創下多項紀錄，顯示高介電氧化物/三五族半導體的異質結構能如同SiO2/Si般具有低介面態位密度與高溫熱穩定性的特性。這樣優異的氧化物/三五半導體異質結構是實現高效能三五族半導體金氧半場效電晶體的關鍵。我們希望這樣的異質結構能在未來矽半導體之外開創不同的研究領域與應用科技。 | zh_TW |
| dc.description.abstract | III-V InGaAs semiconductors hosting high electron mobility have been widely employed in high-speed device applications and condensed matter physics. Recently, high-quality, low trap density high-k/InGaAs heterostructures are urgently demanded in realizing high-performance InGaAs metal-oxide-semiconductor field-effect-transistor (MOSFET) for logic devices, high-speed radio-frequency applications, and further quantum computation. Nonetheless, the grand challenges to realize high-performance InGaAs MOSFETs are the high interface state density (Dit), high border trap density (Nbt), and the low thermal stability of these high-k/InGaAs heterostructures. In this thesis, high-quality high-k/InGaAs heterostructures were demonstrated by in-situ atomic layer deposition (ALD) and molecular beam epitaxy (MBE) grown Y2O3 on various In-content InGaAs semiconductors, from GaAs, In0.2Ga0.8As, to In0.53Ga0.47As. First, we showed that in-situ atomic layer deposited (ALD) Y2O3 was single crystal grown on GaAs(001), which was the first demonstration of single-crystal ALD grown dielectrics on (001)-orientated semiconductors. Excellent crystallinity of 2.3nm-thick ALD-Y2O3 film was confirmed by synchrotron radiation X-ray diffraction. The ALD-Y2O3/GaAs(001) hetero-structure exhibited high thermal stability up to 900oC 60s and a Dit distribution of 1-2x1012 cm-2eV-1 without a mid-gap Dit peak feature; annealing the ALD-Y2O3/GaAs(001) significantly improved the electrical characteristics with considerably reduced frequency dispersion at the accumulation region in capacitance-voltage (CV) characteristics and a Dit down to 2-6x1011 cm-2eV-1, the lowest value among ALD-grown high-k/GaAs(001) heterostructures. The introduction of MBE-Y2O3 further resulted in excellent Y2O3/GaAs(001) and Y2O3/In0.2Ga0.8As(001) interface, which gives symmetric CV characteristics on both p- and n-type (In)GaAs with negligible CV dispersion below 2%/dec, indicative of extremely low Dit and Nbt in high-k/(In)GaAs hetero-structures. The Dit’s extracted by conductance method on both GaAs and In0.2Ga0.8As were extremely low down to 1-3x1011 cm-2eV-1, record-low values for high-k on GaAs and In0.2Ga0.8As(001). Furthermore, lowering the high Dit values, which were up to high-1012 or 1013 cm-2eV-1 near the valence band of high-k/In0.53Ga0.47As as usually attained in previous studies, was considered mission impossible until the demonstration of in-situ Y2O3/In0.53Ga0.47As in this work. The Y2O3/In0.53Ga0.47As interface remained intact with thermal annealing up to 800oC, exhibiting ultra-high thermal stability. The CV characteristics have minimal dispersion of 5% at room temperature and 1% at 77K, respectively. Such well-behaved CVs with negligible dispersion were never reported on p-type In0.53Ga0.47As, indicative of low Dit and low Nbt. Meaningful Dit extraction was also properly discussed using temperature-dependent conductance spectra. The extracted Dit’s were of 3-7x1011 cm-2eV-1 from the valence band to mid-gap region, 1-2 orders of magnitude reduction compared with the previously published works. These achievements have set records in the high-k/III-V research field, demonstrating high-quality high-k/(In)GaAs hetero-structures with low Dit and high thermal stability approaching those in SiO2/Si interface. These perfected high-k/III-V heterostructures are the keys to realizing the ultimate III-V MOSFETs as platforms for basic scientific research studies and device technology beyond Si CMOS technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:50:55Z (GMT). No. of bitstreams: 1 U0001-0508202010345300.pdf: 4756602 bytes, checksum: 55914dbc5e28ef1a3d7db67b2665c95a (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 i 誌謝 ii 中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES xi LIST OF TABLES xvi Chapter 1 Introduction 1 1.1 Si MOS devices and the SiO2/Si interface 1 1.2 Motivation for III-V MOS devices 1 1.2.1 High-performance logic applications 2 1.2.2 Radio-Frequency applications 3 1.2.3 Fundamental physics study and quantum computing devices 4 1.3 Review of III-V surface passivation and the challenges 5 1.4 Organization of this thesis 8 1.5 Contribution of this thesis 9 Chapter 2 Experiment 11 2.1 Multi-chamber system and sample growth 11 2.1.1 III-V Molecular Beam Epitaxy 11 2.1.2 MBE high-k dielectric deposition 15 2.1.3 ALD high-k dielectric deposition 15 2.1.4 Reflection high energy electron diffraction (RHEED) 17 2.2 Electrical measurements 17 2.2.1 MOS capacitor fabrication 18 2.2.2 Dit from Temperature-dependent conductance-voltage method 18 2.2.3 Dit from Quasi-static capacitance-voltage (QSCV) method 20 Chapter 3 Single crystal ALD-Y2O3 on GaAs(100) and GaAs(111)A 21 3.1 In-situ RHEED images 21 3.2 Synchrotron Radiation X-ray diffraction 24 3.3 Electrical Properties 29 3.4 Conclusion 30 Chapter 4 Perfecting ALD-Y2O3/GaAs hetero-structure by UHV annealing 32 4.1 Experimental 33 4.2 In-situ RHEED and XPS 34 4.3 Record-low Dit on ALD-grown high-k/GaAs(100) heterostructure 38 4.4 Comparative study of rapid-thermal annealing ambient 40 4.5 Conclusion 46 Chapter 5 High-quality MBE-Y2O3/InxGa1-xAs(100) (x=0, 0.2) heterostructures with low trap density 47 5.1 MBE-Y2O3 on GaAs(001) 47 5.1.1 CV characteristics 48 5.1.2 Dit distribution and discussion 51 5.1.3 Benchmarking of GaAs(001) MOSCAPs and Dit’s 55 5.2 MBE-Y2O3 on In0.2Ga0.8As(001) 58 5.2.1 Sample growth and RHEED 59 5.2.2 CV and Dit analysis 60 5.2.3 Benchmarking of In0.2Ga0.8As MOSCAPs 62 5.3 Summary and conclusion 65 Chapter 6 Extremely low defect density MBE-Y2O3/In0.53Ga0.47As(100) heterostructure 66 6.1 High thermal stability Y2O3/In0.53Ga0.47As(001) interface 67 6.1.1 Cross-Section STEM studies 67 6.2 In0.53Ga0.47As MOS Electrical characteristics 69 6.2.1 CV characteristics 69 6.2.2 Dit extraction by temperature-dependent conductance method 71 6.2.3 Dit distribution of Y2O3/In0.53Ga0.47As 76 6.3 Summary and conclusion 78 Chapter 7 Conclusions and Outlook 80 7.1 Conclusions 80 7.2 Outlook for future work 81 REFERENCES 82 Appendix 90 Publication List 90 Investigation of interface characteristics of Y2O3/GaSb(001) grown by MBE and ALD 97 | |
| dc.language.iso | en | |
| dc.subject | 介面態位密度 | zh_TW |
| dc.subject | 高介電氧化物 | zh_TW |
| dc.subject | 金氧半異質結構 | zh_TW |
| dc.subject | 三五族半導體 | zh_TW |
| dc.subject | 砷化鎵 | zh_TW |
| dc.subject | 砷化銦鎵 | zh_TW |
| dc.subject | interface state density (Dit) | en |
| dc.subject | High-k dielectrics | en |
| dc.subject | Metal-Oxide-Semiconductor (MOS) heterostructure | en |
| dc.subject | III-V semiconductors | en |
| dc.subject | GaAs | en |
| dc.subject | InGaAs | en |
| dc.title | 高品質高介電氧化物/三五族半導體金氧半結構-超越矽互補式電晶體之科學與科技研究平台 | zh_TW |
| dc.title | High-quality high-k/III-V MOS heterostructures -platforms for science and technology beyond Si CMOS | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.author-orcid | 0000-0002-0757-4109 | |
| dc.contributor.coadvisor | 郭瑞年(Jueinai Kwo) | |
| dc.contributor.oralexamcommittee | 綦振瀛(Jen-Inn Chyi),郭治群(Jyh-Chyurn Guo),胡振國(Jenn-Gwo Hwu),皮敦文(Tun-Wen Pi),陳仕鴻(Szu-Hung Chen) | |
| dc.subject.keyword | 高介電氧化物,金氧半異質結構,三五族半導體,砷化鎵,砷化銦鎵,介面態位密度, | zh_TW |
| dc.subject.keyword | High-k dielectrics,Metal-Oxide-Semiconductor (MOS) heterostructure,III-V semiconductors,GaAs,InGaAs,interface state density (Dit), | en |
| dc.relation.page | 106 | |
| dc.identifier.doi | 10.6342/NTU202002436 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-08-06 | |
| dc.contributor.author-college | 理學院 | zh_TW |
| dc.contributor.author-dept | 物理學研究所 | zh_TW |
| dc.date.embargo-lift | 2025-08-06 | - |
| 顯示於系所單位： | 物理學系 | |
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