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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 簡韶逸(Shao-Yi Chien) | |
dc.contributor.author | Kai Chen | en |
dc.contributor.author | 陳凱 | zh_TW |
dc.date.accessioned | 2021-07-11T14:39:58Z | - |
dc.date.available | 2022-02-21 | |
dc.date.copyright | 2017-02-21 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-01-25 | |
dc.identifier.citation | [1] P. E. Debevec and J. Malik, “Recovering high dynamic range radiance maps from photographs,” in Proceedings of ACM SIGGRAPH, Aug. 1997.
[2] D. Glasner, S. Bagon, and M. Irani, “Super-resolution from a single image,” in 2009 IEEE 12th International Conference on Computer Vision, pp. 349-356 [3] Sony PlayMemories, www.playmemoriescameraapps.com. [4] J. L. Hennessy and D. A. Patterson, “Computer Architecture: A Quantitative Approach,” 3E, pp. 394. [5] R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis and M. Horowitz, 'Understanding sources of inefficiency in general-purpose chips,' in Proceedings of the 37th Annual International Symposium on Computer Architecture, 2010, pp. 37–47 [6] W. Rabadi, R. Talluri, K. Illgne, J. Liang, and Y. Yoo, “Programmable DSP platform for digital still cameras,” in Proceedings 1999 IEEE International Conference on Acoustics and Speech and Signal Processing , Mar. 1999, pp. 2235-2238. [7] I. Kuon and J. Rose, “Measuring the Gap Between FPGAs and ASICs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, Feb. 2007 [8] J. C. Chen and S.-Y. Chien “CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders,” in IEEE Transactions on Circuits and Systems for Video Technology, vol.18, no. 9, Sep. 2008. [9] T.-H. Chen, J C. Chen, T-.Y. Cheng and S.-Y. Chien, “CRISP-DS: Dual-stream coarse-grained reconfigurable image stream processor for HD digital camcorders and digital still cameras,” in Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian [10] T.-Y. Cheng, L.-G. Chen and S.-Y. Chien, 'CRISP-II: Coarse-grained reconfigurable image stream processor for image-processing and intelligent operations in QFHD video cameras,' in Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian [11] J. R. Kelley, C. Barnes, A. Adams, S. Paris, F. Durand and S. Amarasinghe, “Halide: A Language and Compiler for Optimizing Parallelism, Locality, and Recomputation in Image Processing Pipeline,” in Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 519-530, 2013 . [12] J. Hegarty, J. Brunhaver, Z. DeVito, J. R. Kelly, N. Cohen, S. Bell and A. Vasilyev, “Darkroom: Compiling High-Level Image Processing Code into Hardware Pipelines,” in Proceedings of SIGGRAPH 2014 [13] B.E. Bayer, “Color imaging array,” U. S. Patent 3,971,065. [14] V. Betz, J. Rose and A. Marquardt, “Architecture and CAD for Deep-Submicron FPGAs,’ pp. 149, 1999. [15] A. Dunlop and B. Kernighan, “A Procedure for Placement of Standard-Cell VLSI Circuits, ” in IEEE Trans. On CAD, Jan. 1985, pp. 92-98 [16] D. Huang and A. Kahng, “Partitioning-Based Standard-Cell Global Placement with an Exact Objective,” in ACM Symp. On Phtsical Design, 1997, 99. 18-25 [17] J. Kleinhans, G. Sigl, F. Johannes and K. Antreich, “Gordian: VLSI Placement by Quadratic Programming and Slicing Optimization,” in IEEE Trans. On CAD, March 1991, pp. 356-365 [18] G. Sigl, K. Doll and F. Johannes, “Analytical Placement: A Linear or a Quadratic Objective Function?,” in DAC, 1991, pp. 427-432 [19] S. Kirkpatrick, C. Gelatt and M. Vecchi, “Optimization by Simulated Annealing,” in Science, May 13, 1983, pp. 672-680 [20] C. Sechen and A. Sangiovanni-Vincentelli, “TimberWolf3.2: A New Standard Cell Placement and Global Routing Package,” in DAC, 1986, pp. 432-439 [21] C. Ebeling, L. McMurchie, S. A. Hauck and S. Burns, “Placement and Routing Tools for the Triptych FPGA,” in IEEE Trans. on VLSI, Dec. 1995, pp. 473-482 [22] S. Nag and R. Rutenbar, “Performance-Driven Simultaneous Place and Route for Island-Style FPGAs,” in ICCAD, 1995, pp. 332-338 [23] Y. Chang, S. Thakur, K. Zhu and D. Wong, “A New Global Routing Algorithm for FPGAs,” in ICCAD, 1994, pp. 356-361 [24] S. Brown, J. Rose and Z. G. Vranesic, “A Detailed Router for Field-Programmble Gate Arrays,” in IEEE Trans. on CAD, May 1992, pp. 620-628 [25] E. Dijkstra, “A Note on Two Problems in Connexion with Graphs,” in Numer. Math., vol. 1, 1959, pp. 269-271 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78024 | - |
dc.description.abstract | 半導體技術的發展以及移動式裝置的普及帶給影像處理新的挑戰。影像處理器必須有能力實時的處理高解析度影像,並且盡可能的減少能源的消耗。新的影像處理演算法逐年被提出,因此影像處理器必須要有能力支援這些新的演算法。現有的解決方案無法同時達成以上所有的要求。數位訊號處理器為基底的解決方案無法達到實時要求。特殊應用積體電路的功能在晶片下線後便無法再被更改。雖然CRISP-II [10] 架構達到實時要求並且提供了一定程度的可重構性,其彈性仍然是不足的。
在這篇論文當中,下一個世代的CRISP處理器被提出。結合島嶼風格的現場可程式邏輯閘陣列之繞線結構與粗粒度可重構處理單元,被提出的新架構能夠同時滿足實時要求以及彈性需求。特定領域應用語言與電腦輔助設計工具亦被提出。應用被以這種語言撰寫,電腦輔助工具自動將程序翻譯成位元流。位元流被用以將處理器重構為執行目標應用。這套流程提供了開發者一個方便的方法將新的應用映射到既有的處理器上。 | zh_TW |
dc.description.abstract | The advance of CMOS technology and the proliferation of battery powered devices give challenges to image stream processing. Image stream processor should have the ability to process high resolution image in real time, and consume energy as low as possible. New image processing algorithms are proposed year by year, the processor should have the ability to map new applications on it. Existing solutions cannot meet all of the requirements. DSP-based solution cannot meet real time requirement. The functionality of ASIC solution cannot be reconfigured after tapeout. While CRISP-II [10] architecture meets real time requirement and provides some sort of reconfigurability, it is still not flexible enough.
In this thesis, the next generation CRISP architecture is proposed. Combining the routing architecture of island-style FPGA and coarse-grained reconfigurable processing elements, the proposed architecture meets both real time requirement and flexibility requirement. Domain specific language and CAD tools are also proposed. Application is written in this language, and the CAD tools automatically translate program into bitstream which is used to configure target device. The software flow provides an easy way for developers to map new application on target processor. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:39:58Z (GMT). No. of bitstreams: 1 ntu-106-R03943018-1.pdf: 1977634 bytes, checksum: ceceefd5be031f2c08bf32acbec0bcfc (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | 口試委員會審定書 #
中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Existing Solutions 2 1.1.1 Microprocessor 2 1.1.2 Application Specific Integrated Circuit 2 1.1.3 Field Programmable Gate Array 3 1.1.4 Coarse-grained Reconfigurable Image Stream Processor 4 1.2 Image Processing Language 4 1.3 Contribution 5 1.4 Thesis Organization 6 Chapter 2 Background and Previous Work 7 2.1 Image Processing Pipeline 7 2.1.1 Line-buffered Pipeline 8 2.1.2 Stage Scheduling 9 2.1.3 Finding Optimal Scheduling 10 2.2 Coarse-grained Reconfigurable Image Stream Processor 11 2.2.1 Processor Architecture 11 2.2.2 Reconfigurable Stage Processing Element 12 2.2.3 Reconfigurable Stage Interconnection Element 13 2.3 Field Programming Gate Array 14 2.3.1 Architecture 14 2.3.2 Software Flow 16 2.3.3 Placement 17 2.3.4 Routing 18 Chapter 3 Programming Model and Processor Architecture 22 3.1 Programming Model 22 3.1.1 Programming Language 22 3.1.2 Modeling Line-buffered Pipeline 25 3.2 Processor Architecture 26 3.2.1 Arithmetic Block 27 3.2.2 Adaptive Block 28 3.2.3 Buffer Block 29 3.2.4 Line-buffer Block 29 3.2.5 Lookup Table Block 30 3.2.6 Controller Block 31 Chapter 4 CAD Tools 32 4.1 System overview 32 4.2 Block Library 33 4.2.1 DAG Library 34 4.2.2 CGRA Library 35 4.3 Floorplan Generation 36 4.3.1 Visualization 37 4.4 Compilation 38 4.4.1 Semantic Analysis 39 4.4.2 DAG Synthesis 40 4.4.3 Placement and Routing 42 4.5 ASIC Generation 42 Chapter 5 Comparison 43 5.1 Target Image Processing Pipeline 43 5.2 Compared with ASIC and FPGA 44 5.3 Compared with CRISP-II 45 5.4 Compare Different Floorplans 45 Chapter 6 Conclusion 47 REFERENCE 48 | |
dc.language.iso | en | |
dc.title | 可重組化影像處理器及其電腦輔助設計工具 | zh_TW |
dc.title | CRISP-III: Coarse-grained Reconfigurable Image Stream Processor with CAD Tools | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊家驤(Chia-Hsiang Yang),黃朝宗(Chao-Tsung Huang),楊佳玲(Chia-Lin Yang) | |
dc.subject.keyword | 影像處理,特定領域語言,架構設計, | zh_TW |
dc.subject.keyword | Image processing,Domain-specific language,Architecture design, | en |
dc.relation.page | 50 | |
dc.identifier.doi | 10.6342/NTU201700234 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-01-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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