請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77921完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
| dc.contributor.author | Zhan-Ling Wang | en |
| dc.contributor.author | 王占翎 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:37:27Z | - |
| dc.date.available | 2022-08-30 | |
| dc.date.copyright | 2017-08-30 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-08-10 | |
| dc.identifier.citation | [1] 2015 International technology roadmap for semiconductors, http://www.itrs2.net/itrs-reports.html/.
[2] GUROBI Optimizer, http://www.gurobi.com/. [3]Y. Badr, A. Torres, and P. Gupta, “Mask assignment and DSA grouping for DSA-MP hybrid lithography for sub-7 nm contact/via holes,” IEEE Transac- tions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 913–926, 2017. [4]X.-Y. Bao, H. Yi, C. Bencher, L.-W. Chang, H. Dai, Y. Chen, P.-T. J. Chen, and H.-S. P. Wong, “SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical tem- plates,” in Proceedings of IEEE International Electron Devices Meeting, pp. 7.1.1–7.1.4, Washington, DC, December 2011. [5]J.-B. Chang, H. K. Choi, A. F. Hannon, A. Alexander-Katz, C. A. Ross, and K. K. Berggren, “Design rules for self-assembled block copolymer patterns using tiled templates,” Nature communications, vol. 5, p. 3305, 2014. [6]Y. Ding, C. Chu, and W.-K. Mak, “Throughput optimization for SADP and e- beam based manufacturing of 1D layout,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 51:1–51:6, San Francisco, CA, June 2014. [7]Y. Du, D. Guo, M. D. Wong, H. Yi, H.-S. P. Wong, H. Zhang, and Q. Ma, “Block copolymer directed self-assembly (DSA) aware contact layer optimiza- tion for 10 nm 1d standard cell library,” in Proceedings of IEEE/ACM Inter- national Conference on Computer-Aided Design, pp. 186–193, San Jose, CA, November 2013. [8]S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, “A novel layout decomposition algorithm for triple patterning lithography,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 33, no. 3, pp. 397–408, 2014. [9]S.-Y. Fang, Y.-X. Hong, and Y.-Z. Lu, “Simultaneous guiding template opti- mization and redundant via insertion for directed self-assembly,” IEEE Trans- actions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp. 156–169, 2017. [10]A. F. Hannon, Y. Ding, W. Bai, C. A. Ross, and A. Alexander-Katz, “Opti- mizing topographical templates for directed self-assembly of block copolymers via inverse design simulations,” Nano letters, vol. 14, no. 1, pp. 318–325, 2013. [11]S.-J. Jeong, J. Y. Kim, B. H. Kim, H.-S. Moon, and S. O. Kim, “Directed self-assembly of block copolymers for next generation nanolithography,” Mate- rials Today, vol. 16, no. 12, pp. 468–476, 2013. [12]J. Kuang, J. Ye, and E. F. Young, “Simultaneous template optimization and mask assignment for DSA with multiple patterning,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 75– 82, Macao, January 2016. [13]J. Kuang, E. F. Young, and B. Yu, “Incorporating cut redistribution with mask assignment to enable 1D gridded design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 48:1–48:8, Austin, TX, November 2016. [14]Z.-W. Lin and Y.-W. Chang, “Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 89–94, Macao, Jan- uary 2016. [15]——, “Double-patterning aware DSA template guided cut redistribution for ad- vanced 1-D gridded designs,” in Proceedings of ACM International Symposium on Physical Design, pp. 47–54, Santa Rosa, CA, April 2016. [16]Y. Ma, J. A. Torres, G. Fenger, Y. Granik, J. Ryckaert, G. Vanderberghe, J. Bekaert, and J. Word, “Challenges and opportunities in applying grapho- epitaxy DSA lithography to metal cut and contact/via applications,” in Pro- ceedings of SPIE, vol. 9231, pp. 92 310T–92 310T–10, 2014. [17]J. Ou, B. Yu, J.-R. Gao, D. Z. Pan, M. Preil, and A. Latypov, “Directed self-assembly based cut mask optimization for unidirectional design,” in Pro- ceedings of the Great Lakes Symposium on VLSI, pp. 83–86, Pittsburgh, PA, May 2015. [18]Y.-H. Su and Y.-W. Chang, “DSA-compliant routing for two-dimensional pat- terns using block copolymer lithography,” in Proceedings of IEEE/ACM In- ternational Conference on Computer-Aided Design, pp. 50:1–50:8, Austin, TX, November 2016. [19]——, “Nanowire-aware routing considering high cut mask complexity,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 964–977, 2016. [20]H.-S. P. Wong, C. Bencher, H. Yi, X.-Y. Bao, and L.-W. Chang, “Block copoly- mer directed self-assembly enables sublithographic patterning for device fabri- cation,” in Proceedings of SPIE, vol. 8323, pp. 832 303–832 303–7, 2012. [21]Z. Xiao, Y. Du, H. Tian, M. D. Wong, H. Yi, and H.-S. P. Wong, “DSA template optimization for contact layer in 1D standard cell design,” in Proceedings of SPIE, vol. 9049, pp. 904 920–904 920–8, 2014. [22]Z. Xiao, Y. Du, M. D. Wong, and H. Zhang, “DSA template mask determination and cut redistribution for advanced 1D gridded design,” in Proceedings of SPIE, vol. 8880, pp. 888 017–888 017–8, 2013. [23]Y. Zhang, W.-S. Luk, F. Yang, C. Yan, H. Zhou, D. Zhou, and X. Zeng, “Network flow based cut redistribution and insertion for advanced 1D layout design,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automa- tion Conference, pp. 360–365, Chiba, January 2017. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77921 | - |
| dc.description.abstract | 二維自我引導組裝 (two-dimensional directed self-assembly) 是一種次5奈米製程有潛力的候選技術，該技術通過不同的雙重點狀圖樣的組合來確定金屬線的走向。二維自我引導組裝技術中，其運用金屬線末端的切斷點製造出二維圖樣從而獲得想要的線路佈局。同時，為了消除切割光罩之間的距離衝突，它需要重新分佈切斷點的位置。在本篇論文中，我們首次提出方法解決二維自我引導組裝中的切斷點重新分佈的問題。首先，我們將這個問題表述成一個整數線型規劃問題，從而獲得一個最佳解。其次，我們提出一個基於完整模板候選者建立的圖的演算法。邊代表的是模板候選者之間的衝突，這些衝突會在線性時間內被計算。該演算法具有保持最優解的性質，能夠轉化二維自我引導組裝中的切斷點重新分佈問題。它將切斷點重新分佈問題化簡成一個是否選取某個模板候選者的問題，從而被表述成一個二元整數線性規劃問題。這可以被證明是一個很好的方案去更好的處理切斷點重新分佈問題。實驗結果顯示，我們的基於圖的演算法具有高品質與高效率。與基於整數線性規劃的演算法相比，我們基於圖的演算法在切割光罩距離衝突消除和金屬線延長長度最小化兩方面達到最佳解的同時，在速度上平均較快1002倍。 | zh_TW |
| dc.description.abstract | Two-dimensional (2D) directed self-assembly (DSA) is a promising candidate for sub-5nm process technology, which generates routes through various combinations of oriented double posts. In 2D DSA, line-end cuts are employed to fabricate 2D patterns to derive desired layouts, and cut redistribution is applied to eliminate cut spacing violations. In this thesis, we present the first work to handle the 2D DSA cut redistribution problem. We first formulate this problem as an integer linear programming (ILP) problem to obtain an optimal solution. We then propose an optimality-preserving framework, based on a complete template candidate graph, to transform the 2D DSA cut redistribution problem. The spacing violations between template candidates, which are represented as edges, are evaluated in linear time. This framework simplifies the cut redistribution problem to selecting a template candidate or not, which formulates a binary ILP to provide a provably good scheme to better handle cut redistribution problem. Experimental results demonstrate that our graph-based algorithm can effectively and efficiently redistribute cuts with zero spacing violations and minimum wire extensions. Compared with the ILP-based algorithm, our graph-based algorithm can achieve 1002 times faster on average. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:27Z (GMT). No. of bitstreams: 1 ntu-106-R04943155-1.pdf: 3563469 bytes, checksum: 2746d74b4b2be59c6204968164ead7e2 (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | Table of Contents
Acknowledgements iii Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Two-Dimensional Directed Self-Assembly . . . . . . . . . . . . . . . . . 1 1.2 2D DSA Cut Redistribution Problem . . . . . . . . . . . . . . . . . . . . 5 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2. Preliminaries 11 2.1 2D Pattern Extension Rules . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 DSA Cut Template Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Cut Template Candidate Construction . . . . . . . . . . . . . . . . . . . 15 2.4 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3. ILP-Based Algorithm 22 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 Wire Extension Constraint . . . . . . . . . . . . . . . . . . . . . . 24 3.3.2 Template Violation Constraint . . . . . . . . . . . . . . . . . . . . 25 3.3.3 Internal Cut Spacing Constraint . . . . . . . . . . . . . . . . . . . 26 3.3.4 Line-end Cut Constraint . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.5 Guiding Template Constraint . . . . . . . . . . . . . . . . . . . . . 28 3.4 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 4. Graph-Based Algorithm 30 4.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 Cut Template Candidate Violation Evaluation . . . . . . . . . . . . . . . 32 4.3 Template Candidate Violation Graph Construction . . . . . . . . . . . . 36 4.4 Complete Template Candidate Group Determination . . . . . . . . . . . 38 4.4.1 Binary ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.2 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 Optimality-Preserving Analysis . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 5. Experimental Results 43 5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 Comparison and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 6. Conclusions and Future Work 51 Bibliography 55 | |
| dc.language.iso | en | |
| dc.title | 基於奈米級圖樣針對二維自我引導組裝之切斷點重新分佈 | zh_TW |
| dc.title | Nanoscale Pattern-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江蕙如(Hui-Ru Jiang),方劭云(Shao-Yun Fang),黃婷婷(Ting-Ting Hwang) | |
| dc.subject.keyword | 實體設計,製造可行性設計,二維自我引導組裝,切斷點重新分佈, | zh_TW |
| dc.subject.keyword | Physical Design,Design for Manufacturing,Two-Dimensional Directed Self-Assembly,Cut Redistribution, | en |
| dc.relation.page | 58 | |
| dc.identifier.doi | 10.6342/NTU201702038 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-08-10 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-106-R04943155-1.pdf 目前未授權公開取用 | 3.48 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。