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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77914完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | |
| dc.contributor.author | Ting-Chou Lin | en |
| dc.contributor.author | 林庭州 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:37:18Z | - |
| dc.date.available | 2022-08-31 | |
| dc.date.copyright | 2017-08-31 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-08-10 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77914 | - |
| dc.description.abstract | 整合扇出型晶圓級封裝堆疊 (wafer-level integrated fan-out package-on-package) 是一個大有可為的立體封裝技術，此封裝技術通常會包含一個下層封裝採用整合扇出型晶圓級封裝技術和一個上層封裝堆疊在下層封裝上。與傳統的封裝堆疊不同之處在於，整合扇出型晶圓級封裝有正面和背面兩個多層重分佈層 (redistribution layer) 來進行訊號傳輸。據我們所知，目前尚未有發表的論文是針對處裡整合扇出型晶圓級封裝堆疊中的重分佈層繞線問題。大部分相關的發表論文著重於三種類型的重分佈層繞線問題，分別是自由配對繞線問題、非自由配對繞線問題與混合型配對繞線問題，並且考慮單一或是多個晶片。在此篇論文當中，我們提出了一個新的整合扇出型晶圓級封裝堆疊中的重分佈層繞線問題。為了彌補相關論文缺乏對於正面及背面兩個多層重分佈層的考慮，我們提出了第一個演算法來針對處理整合扇出型晶圓級封裝堆疊中的重分佈層繞線問題，此問題考慮到了訊號線的分層、重分佈層數量的最小化與總線長的最小化。我們提出了一個抽取多個遞增子序列 (increasing subsequence) 的演算法，這個演算法會轉換一個繞線順序成為兩個有向非循環圖 (directed acyclic graph) ，分別是遞增子序列有向非循環圖和限制有向非循環圖。藉由最小化在限制有向非循環圖上的最長路徑當中的節點數量，我們可以適當的減少重分佈層的數量。除此之外，我們會在遞增子序列有向非循環圖使用回朔法來將連線分配到適當的重分佈層來避免訊號線過長。實驗結果顯示我們的繞線器可以達到百分之百的繞線率，相較之下，相關發表論文所延伸的演算法無法達到百分之百的繞線率，並且會使用更多的正面多層重分佈層。 | zh_TW |
| dc.description.abstract | The wafer-level integrated fan-out (InFO) package-on-package (PoP) is a promising 3D packaging technology, which usually consists of a bottom package with the InFO technique, and a top package stacked on the bottom package.Different from the traditional PoPs, there are frontside and backside redistribution layers (RDLs) in the InFO PoP for signal redistributions.To the best of our knowledge, there is still no previous work specifically tackling the RDL routing for the InFO PoP.Previous works on RDL routing mainly deal with the following three types of routing: the free-assignment, pre-assignment, and unified-assignment routing for single or multiple chips.In this thesis, a new RDL routing problem for the InFO PoP is formulated. To remedy the deficiencies of lacking the interactions between frontside and backside RDLs, we present the first work in the literature to handle the unified-assignment multi-layer multi-package RDL routing problem (without RDL vias), considering layer assignment, layer number minimization, and total wirelength minimization. We propose an algorithm based on extracting increasing subsequences (IS), which transforms a routing sequence into two directed acyclic graphs (DAGs), namely, IS-DAG and Constraint-DAG.By minimizing the number of vertices on the longest path on the Constraint-DAG, we implicitly minimize the layer number.Furthermore, we perform backtracking on the IS-DAG to efficiently assign the connections to appropriate layers to avoid long detours.Experimental results show that our router can achieve 100% routablility for all given test cases, while the previous works with extensions fail all test cases even with more frontside RDLs. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:18Z (GMT). No. of bitstreams: 1 ntu-106-R04943101-1.pdf: 2995660 bytes, checksum: 643524f1c4c70cc01644f82df889cd24 (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Wafer-Level Integrated Fan-Out Package-on-Packages . . . . . . . . . . . 1 1.2 RDL Routing for Traditional Flip-Chip . . . . . . . . . . . . . . . . . . . 4 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 Free-Assignment RDL Routing . . . . . . . . . . . . . . . . . . . . 7 1.3.1.1 Network-Flow-Based Approaches . . . . . . . . . . . . . . 7 1.3.1.2 Non-Network-Flow-Based Approaches . . . . . . . . . . . 10 1.3.2 Pre-Assignment RDL Routing . . . . . . . . . . . . . . . . . . . . 10 1.3.2.1 ILP-Based Approaches . . . . . . . . . . . . . . . . . . . 11 1.3.2.2 Non-ILP-Based Approaches . . . . . . . . . . . . . . . . . 11 1.3.3 Unied-Assignment RDL Routing . . . . . . . . . . . . . . . . . . 11 1.3.4 Integrated Fan-Out Packages RDL Routing . . . . . . . . . . . . . 12 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 2. Preliminaries 17 2.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Routing Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3. Our Algorithm 23 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Congestion Estimation on Frontside RDLs . . . . . . . . . . . . . . . . . 26 3.3 Backside RDL Global Routing . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 Ring-by-Ring Routing for Free/Pre-Assignment Nets . . . . . . . 26 3.3.2 Congestion-Aware TIV/Layer Assignment . . . . . . . . . . . . . 32 3.4 Frontside RDL Global Routing . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.1 Pad/Layer Reassignment for Free-Assignment Nets . . . . . . . . 37 Chapter 4. Experimental Results 41 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Comparison and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 5. Conclusions and Future Work 49 Bibliography 54 Publication List 59 | |
| dc.language.iso | en | |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 整合扇出型晶圓級封裝堆疊 | zh_TW |
| dc.subject | 重分佈層 | zh_TW |
| dc.subject | 重分佈層繞線 | zh_TW |
| dc.subject | Wafer-Level Integrated Fan-Out Package-on-Package | en |
| dc.subject | RDL Routing | en |
| dc.subject | Redistribution Layer | en |
| dc.subject | Physical Design | en |
| dc.title | 整合扇出型晶圓級封裝堆疊設計之繞線系統 | zh_TW |
| dc.title | A Redistribution Layer Routing System for Wafer-Level Integrated Fan-Out Package-on-Packages | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 方劭云,江蕙如,黃婷婷 | |
| dc.subject.keyword | 實體設計,整合扇出型晶圓級封裝堆疊,重分佈層,重分佈層繞線, | zh_TW |
| dc.subject.keyword | Physical Design,Wafer-Level Integrated Fan-Out Package-on-Package,Redistribution Layer,RDL Routing, | en |
| dc.relation.page | 59 | |
| dc.identifier.doi | 10.6342/NTU201702852 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-08-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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