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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Cheng-Jia Dai | en |
dc.contributor.author | 戴承家 | zh_TW |
dc.date.accessioned | 2021-07-11T14:37:04Z | - |
dc.date.available | 2022-08-31 | |
dc.date.copyright | 2017-08-31 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-14 | |
dc.identifier.citation | [1] E. Pop, “Energy Dissipation and Transport in Nanoscale Devices,” Nano Res., 3, 147 (2010).
[2] T.-J. K. Liu, “Bulk CMOS Scaling to the End of the Roadmap,” in VLSI Symp. Tech. Dig., short course, 2 (2012). [3] L. Czornomaz, N. Daix1, D. Caimi, M. Sousa, R. Erni, M. D. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart and J. Fompeyrine, “An Integration Path for Gate-first UTB III-V-on-insulator MOSFETs with Silicon, using Direct Wafer Bonding and Donor Wafer Recycling,” in IEDM Tech. Dig., 517 (2012). [4] J. J. Gu, X. W. Wang, J. Shao, A. T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye, “III-V Gate-all-around Nanowire MOSFET Process Technology: From 3D to 4D,” in IEDM Tech. Dig., 529 (2012). [5] J. J. Gu, X. W. Wang, H. Wu, J. Shao, A. T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye, “20-80nm Channel Length InGaAs Gate-all-around Nanowire MOSFETs with EOT=1.2nm and Lowest SS=63mV/dec,” in IEDM Tech. Dig., 633 (2012). [6] P. D. Ye, G.D. Wilk, J. Kwo, B. Yang, H.-J. L. Gossmann, M. Frei, S. N. G. Chu, J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, “GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition,” IEEE Electron Device Lett., 24, 209 (2003). [7] M. M. Frank, G. D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y. J. Chabal, J. Grazul, and D. A. Muller, “HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition,” Appl. Phys. Lett., 86, 152904 (2005). [8] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, “Surface passivation of III–V compound semiconductors using atomic-layer-deposition-grown Al2O3,” Appl. Phys. Lett., 87, 252104 (2005). [9] Y. Urabe, N. Miyata, H. Ishii, T. Itatani, T. Maeda, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Yokoyama, N. Taoka, M. Takenaka, and S. Takagi, “Correlation between Channel Mobility Improvements and Negative Vth Shifts in III-V MISFETs: Dipole Fluctuation as New Scattering Mechanism,” in IEDM Tech. Dig., 142 (2010). [10] A. Kapila and V. Malhotra, “Surface passivation of III-V compound semiconductors,” in Optoelectronic and Microelectronic Materials and Devices Proc., 275 (1996). [11] D. Kim, T. Krishnamohan, Y. Nishi, K. C. Saraswat, “Band to Band Tunneling limited Off state Current in Ultra-thin Body Double Gate FETs with High Mobility Materials : III-V, Ge and strained Si/Ge,” in Simulation of Semiconductor Processes and Devices, 389 (2006). [12] M. Passlack, “OFF-State Current Limits of Narrow Bandgap MOSFETs,” IEEE Trans. Electron Dev., 53, 2773 (2006). [13] K. L. Nummila, Short-channel Effects in III-V Compound Semiconductor Field-effect Transistors, University of Illinois at Urbana-Champaign, 1993. [14] A. Mahajan, M. Arafa, P. Fay, C. Caneau, and I. Adesida, “Enhancement-Mode High Electron Mobility Transistors (E-HEMT’s) Lattice-Matched to InP” IEEE Trans Elec Dev., 45(12), 2422-2429 (1998). [15] É. O’Connor, et al. “A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers.' Journal of Applied Physics 109.2, 024101, (2011). [16] J. J. Gu, A. T. Neal, and P. D. Ye, “Effects of (NH4) 2S passivation on the off-state performance of 3-dimensional InGaAs metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, 99(15), 152113, (2011). [17] Y. Xuan, Y. Q. Wu, and P. D. Ye. 'High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm.' IEEE Electron Device Letters 29.4 (2008): 294-296. [18] D. C. Dumka, H. Q. Tserng, M. Y. Kao, E. A. Beam, III, P. Saunier, 'High-performance double-recessed enhancement-mode metamorphic HEMTs on 4-In GaAs substrates.' IEEE Electron Device Letters24.3 (2003): 135-137. [19] Kevin J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamamoto, 'High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies.' IEEE Transactions on Electron Devices 43.2 (1996): 252-257. [20] A. Mahajan, M. Arafa, P. Fay, C. Caneau, and I. Adesida, '0.3-μm gate-length enhancement mode InAlAs/InGaAs/InP high-electron mobility transistor.' IEEE Electron Device Letters 18.6 (1997): 284-286. [21] N. Harada, S. Kuroda, T. Katakami, K. Hikosaka, T. Mimura, M. Abe, 'Pt-based gate enhancement-mode InAlAs/InGaAs HEMTs for large-scale integration.' Indium Phosphide and Related Materials, 1991., Third International Conference.. IEEE, (1991). [22] T. Suemitsu, H. Yokoyama, Y. Umeda, T. Enoki, and Y. Ishii, 'High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology.' IEEE Transactions on Electron Devices 46.6 (1999): 1074-1080. [23] S. Rathi, J. Jogi, M. Gupta, R.S. Gupta 'Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs–InGaAs symmetric double-gate HEMT.' Microelectronics Reliability 49.12 (2009): 1508-1514. [24] Micro resist technology, “Negative Tone Photoresist Series ma-N 2400” [25] M. A. Mohammad, M. Muhammad, S. K. Dew, and M. Stepanova, “Chapter 2: Fundamentals of Electron Beam Exposure and Development, Nanofabrication Technology and Principles,” (2012). [26] Keysight technology, “Keysight Technologies B1500A Semiconductor Device Analyzer - Configuration and Connection Guide,” 7th edition, (2015). [27] D. K. Schroder, “Semiconductor material and device characterization”, 3rd edition, (2006). [28] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, 'On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration.' IEEE Transactions on Electron Devices 41.12 (1994): 2357-2362. [29] D. Laroche, S. Das Sarma, G. Gervais, M. P. Lilly, and J. L. Reno, 'Scattering mechanism in modulation-doped shallow two-dimensional electron gases.' Applied Physics Letters 96.16 (2010): 162112.'Scattering mechanism in modulation-doped shallow two-dimensional electron gases.' Applied Physics Letters 96.16 (2010): 162112. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77903 | - |
dc.description.abstract | 在本論文中,我們提出一個可以解決三五族電晶體負臨界電壓問題的方法。傳統上可以藉由改變緩衝層厚度、改變電子供應層的位置或濃度、使用硫化氨((NH4)2S)進行表面鈍化以及使用「Pt sinking」技術使得高電子遷移率電晶體(High-electron-mobility transistor)之臨界電壓往正值移動。根據上述,已經有很多團隊藉由不同技術得到高效能常關型(normally-off)高電子遷移率電晶體。在本論文中,我們團隊也成功地在不使得效能衰退的情況下得到常關型(增強型)高電子遷移率電晶體。
首先我們介紹如何使用電子束負光阻ma-N 2403開發出奈米等級顯影圖形,並且成功製作出高深寬比(Aspect ratio, AR)之顯影圖形,其中最小線寬達到42奈米,我們也在乾蝕刻過後得到良好的圖形轉移(Pattern transfer)結果。 接著我們藉由一個四步驟的半導體製程製作出擁有良好開啟及次臨界特性的鰭式砷化銦鎵高電子遷移率電晶體。我們也探討了此電晶體在不同鰭寬度(Fin width)之下之傳輸特性,實驗結果顯示在此元件中庫倫散射(Coulomb scattering)是主要限制等效電子遷移率(Mobility)之機制。 我們也比較了鎳/金以及鈦/鉑/金兩種不同閘極金屬對元件電特性之影響。鎳/金為閘極之元件擁有較好的開啟以及次臨界特性,但是閘極漏電流是將來製作常關型元件中相當關鍵的問題。 再者,我們使用原子層沉積技術(Atomic layer deposition, ALD)結合原本的製程製作出鰭式金氧半高電子遷移率電晶體(Fin-MOSHEMT)以期可以克服閘極漏電流問題。但是由於閘極至通道距離過長以及半導體表面仍然不夠理想使得Fin-MOSHEMT的電特性仍然未比原本的FinHEMT好。 最後,我們分析了閘極側壁對於通道的控制機制,此控制機制是我們能夠成功得到增強型元件且不使得元件電特性衰退的主因。主因為:元件的通到會先被閘極側壁完全空乏(fully-depleted)早於被上方閘級關閉,因此,我們可以僅僅改變鰭寬度得到有良好開啟特性以及次臨界特性的電晶體。 | zh_TW |
dc.description.abstract | In the thesis, we propose a new approach to overcome the negative threshold voltage issue for III-V transistors. Traditionally, threshold voltage can be modulated toward +VG direction by changing the thickness of barrier, changing the position or concentration of delta-doping layer, passivating the surface material of gate region by ammonium sulfide (NH4)2S or utilizing Pt-sinking technology for High-electron-mobility transistors. Lots of successful results were carried out to achieve high-performance enhancement-mode (normally-off) transistors so far. In this thesis we successfully fabricated E-mode transistors without performance degradation.
First we introduce the development of negative photoresist ma-N 2403 which has the ability to creative nanoscale pattern. We successfully scaled down the high-aspect-ratio fin width to about 42 nm. The results also show excellent pattern transfer capability after dry etch. Then we carried out the fabrication by a 4-step process. InGaAs FinHEMTs were fabricated with high on-state and subthreshold performance. Moreover, we investigated the transport properties of InGaAs FinHEMTs with different fin width. The experimental results show that Coulomb scattering is dominant limiting term for effective mobility. We also compared the devices whose gate stack are Ni/Au and Ti/Pt/Au respectively. Ni/Au-gated devices show better on-state and subthreshold performance but the gate leakage issue becomes a critical issue for E-mode devices. Furthermore, we incorporated ALD-deposited Al2O3 to fabricate InGaAs Fin-MOSHEMT. The performance is much worse than FinHEMT’s because the distance between gate and channel is too large and the quality of surface is poor. Last, we analyze the mechanism of sidewall control of gate which can achieve E-mode transistors without any performance degradation. The channel is fully depleted by depletion regions from sidewall of gate much earlier than top gate does. Hence, E-mode transistors can be simply achieved by varying the size of fin width with excellent on-state and subthreshold performance. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:04Z (GMT). No. of bitstreams: 1 ntu-106-R04943055-1.pdf: 5245265 bytes, checksum: 1029e852aeae967443b8cd87a64e9738 (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | 口試委員審定書 I
誌謝 II 摘要 III Abstract V Table of Contents VII List of Figures XI List of Tables XVI Chapter 1. Introduction 1 1.1. On the Scaling Limit of Planar Si MOSFETs 1 1.2. Development of III-V CMOS 3 1.3. High-speed III-V devices 5 1.4. Organization of work 7 Chapter 2. Development and Fabrication of Nanoscale InGaAs Fin-shaped High-Electron-Mobility Transistors (Fin-HEMTs) 8 2.1. Preface 8 2.2. Background and development 9 2.2.1. Properties of III-V materials 9 2.2.2. Introduction to High-electron-mobility transistors (HEMTs) 10 2.3. Fabrication process of InGaAs Fin-shaped High-electron-mobility transistors (InGaAs Fin-HEMTs) 12 2.3.1. Introduction to ma-N 2403 photoresist 12 2.3.2. E-beam pattern design of fin structure 13 2.3.3. Layer structure of HEMT 17 2.3.4. Device fabrication process 17 2.4. Electrical characteristics of InGaAs FinHEMTs 22 2.4.1. Experimental setup 22 2.4.2. TLM and I-V characteristics of InGaAs FinHEMT 23 2.5. Comparison of electrical characteristics of InGaAs FinHEMTs with different fin width (Wfin) 28 2.5.1. Comparison of transfer characteristics 28 2.5.2. Comparison of subthreshold performance and process stability 28 2.6. Brief summary of this chapter 29 Chapter 3. Investigation of Transport Properties at On-state Operation of Fin-shaped High-electron-mobility Transistors 33 3.1. Preface 33 3.2. Method of Mobility Extraction for InGaAs FinHEMTs 34 3.2.1. Split-CV method 34 3.2.2. On-resistance and channel resistance 38 3.2.3. Effective VDS on channel region 41 3.2.4. Procedure of extracting mobility of InGaAs FinHEMTs 42 3.3. Results of Mobility Extraction for InGaAs FinHEMTs 44 3.3.1. Measurements at room temperature (T ~ 300k) 44 3.3.2. Relation between scattering and carrier mobility 46 3.3.3. Analysis of scattering on effective mobility 48 3.4. Investigation of Mobility at Different Temperature 51 Chapter 4. Analysis of Subthreshold Performance and Mechanism of Gate Sidewall Control of InGaAs FinHEMTs with Different Gate Stack 55 4.1. Preface 55 4.2. Electrical characteristics of different gate metal 56 4.2.1. Gate-to-drain diode 56 4.2.2. Gate leakage issue of Ni/Au contact 57 4.2.3. Comparison of electrical characteristics 60 4.3. Fabrication and electrical characteristics of InGaAs-based Fin-MOSHEMTs 63 4.4. Analysis of gate control mechanism of InGaAs –based Fin-HEMTs 67 4.4.1. Throwback to Chapter 2.5 67 4.4.2. Simulation of depletion width by Silvaco TCAD 68 4.4.3. Investigation of gate control mechanism of InGaAs Fin-shaped HEMTs (FinHEMTs) 70 Chapter 5. Conclusion 75 References 77 | |
dc.language.iso | en | |
dc.title | 砷化銦鎵鰭式高載子遷移率電晶體之製作與傳輸特性及閘極控制機制之研究 | zh_TW |
dc.title | Fabrication and Investigation of the Transport Properties and Gate Control Mechanism of Nanoscale InGaAs-based Fin-shaped High Electron Mobility Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃建璋(Jian-Jang Huang),陳敏璋(Miin-Jang Chen),張書維(Shu-Wei Chang) | |
dc.subject.keyword | 臨界電壓,高電子遷移率電晶體,增強型,等效電子遷移率,散射效應,空乏區, | zh_TW |
dc.subject.keyword | Threshold voltage,High-electron-mobility transistor,enhancement mode,effective mobility,scattering effect,depletion region, | en |
dc.relation.page | 81 | |
dc.identifier.doi | 10.6342/NTU201703012 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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