設計適用於可容忍變異微處理器之可偵測及更正時序錯誤系統

Abstract

比起以往，現代穿戴式裝置日新月異的應用在功能變強的同時也使得功率消耗變得更加巨大，如何在有限的電池容量下延長裝置的使用時間是個重要的議題；根據裝置目前的狀態和應用使用動態電壓頻率調整(DVFS)的技術可以有效的降低能量消耗。但在先進製程中，製程、電壓、溫度、老化等變異的影響越來越嚴重，尤其是在極低操作電壓下，變異除了導致效能下降，甚至能使電路失去作用。為了克服在低操作電壓下變異的影響，本論文提出了一個能偵測時序錯誤並起更正的系統，包含一能偵測且自動修復的正反器元件(EDAC)，以及能在處理器階段的更正，像是指令中斷及重做。此外未來此系統也能和動態電壓頻率調整的技術結合，更進一步使因變異造造成的影響減少，進而克服在低電壓操作的挑戰。另一方面，此論文亦對現有的標準元件庫在目標操作電壓下重新提取特性，提取時只選出其中較為擁有強韌性的元件，使其最低操作電壓可在400mV，並能夠確保在低電壓下的元件的正確性；此外同時也把此EDAC融入到一般標準元件庫設計流程，使得設計模擬能從電晶體層次提升至閘位準層次，以節省模擬時間。應用在ARM Coretex-M0 微處理器並且使用TSMC-28nm製程。模擬結果顯示，所提出之設計能得到更佳的能源使用率。

As modern wearable devices having more powerful performances than past, their power consumption is rapidly growing. To increase the battery life with limited capacity is significant issue. According to the requirement needed now, dynamic voltage frequency scaling (DVFS)is an efficient technique. However, in the advanced technology (under 40nm) , the process, voltage, temperature and ageing (PVTA) variations can cause huge impact on circuits performance even their functionality with operating in ultra-low voltage(ULV). To overcome the effect of variations, this thesis proposes an error detection and correction (EDAC) system. The system has two level correction mechanism : cell level and processor level. In cell level, an error resilient flip-flop be using, which can detect and correct the timing error automatically in cell level. Furthermore, when the error can not be corrected by cells, the system can combine with DVFS and instruction replay. In the other hand, an existing standard cell library is re-characterized in target operating voltage. Only the robust cells are selected to be sure that the remains are able to operate at 400mV. The design are verified and fabricated using TSMC-28nm on ARM Cotex-M0 MCU. The simulation results show that it has better energy efficiency with the proposed method.