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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Tse-Kai Chen | en |
dc.contributor.author | 陳則凱 | zh_TW |
dc.date.accessioned | 2021-07-10T22:09:26Z | - |
dc.date.available | 2021-07-10T22:09:26Z | - |
dc.date.copyright | 2018-08-08 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-08-06 | |
dc.identifier.citation | [1] Chin-Khai Tang, Ming-Shing Su, and Yi-Chang Lu, “LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems,” IEEE Signal Processing Letters, Vol. 20, No. 7, July 2013.
[2] M. J. Wieland H. Derks H. Gupta T. van de Peut F. M. Postma A. H. V. van Veen Y. Zhang 'Throughput enhancement technique for MAPPER maskless lithography' Proc. SPIE vol. 7637 Apr. 2010. [3] P. Petric C. Bevis A. Brodie A. Carroll A. Cheung L. Grella M. McCord H. Percy K. Standiford M. Zywno 'REBL nanowriter: Reflective electron beam lithography' Proc. SPIE vol. 7271 Mar. 2009. [4] Jacob Ziv, Abraham Lempel, 'A Universal Algorithm for Sequential Data Compression'. IEEE Transaction on Information Theory, Vol. IT-23, No. 3, May 1977. [5] V. Dai, “Data Compression for Maskless Lithography Systems: Architecture, Algorithms and Implementation,” Ph.D. dissertation, University of California, Dept. Electrical Engineering Computer Science, Berkeley, CA, USA, 2008. [6] Martin Feldman, Nano lithography: Nanolithography the art of fabricating nanoelectronic and nanophotonic devices and systems, 1st ed. Oxford: Woodhead Publishing, 2014 [7] Die Per Wafer Estimator provided by Silicon Edge http://www.silicon-edge.co.uk/j/index.php/resources/die-per-wafer [8] Ming-Shing Sua, Kuen-Yu Tsaia, Yi-Chang Lua, Yu-Hsuan Kuoa, Ting-Hang Peia, and Jia-Yush Yenb, “Architecture for next generation massively parallel maskless lithography system (MPML2),” Proc. SPIE, Vol. 7637, Alternative Lithographic Technologies II, 76371Q, Apr. 2010. [9] Jeehong Yang, “Lossless Circuit Layout Image Compression Algorithm for Multiple Electron Beam Direct Write Lithography Systems,” Ph.D. dissertation, University of Michigan, 2012. [10] Marc Levoy, 'Introduction to computer graphics: Raterization algorithm' Autumn Quarter 2008. Lecture notes [online] Available: http://graphics.stanford.edu/courses/cs248-08/scan/scan1.html [11] Kevin Weiler Peter Antherton 'Hidden surface removal using polygon area sorting' Proc. of SPIE 5992 vol. 11 pp. 214-222 1977. [12] Steve DiBartolomeo, “All About Calma's GDSII Stream Format”. Available: http://www.artwork.com/gdsii/gdsii/index.htm [13] Klayout: a layout viewer and editor. Available: https://www.klayout.de/ [14] Yu-Hsiang Chiu, “Data Compression Ratio-aware Detailed Routing for Multiple E-Beam Direct Write Systems” Thesis of National Taiwan University, Sep. 2015. [15] Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin, “An Instruction-based High-Throughput Lossless Decompression Algorithm for E-Beam Direct-Write System,” Proc. SPIE, vol. 9423, Alternative Lithographic Technologies VII, 94231P, Mar. 2015. [16] Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, “Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),” 1st Edition, Elsevier Inc., 2009, Chapter 12. [17] Jeehong Yang, Serap A. Savari, “Lossless circuit layout image compression algorithm for maskless direct write lithography systems,” in Proc. SPIE. vol.10 043007-1, doi:10.1117/1.3644620, Dec, 2011 [18] Shy-Jay Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Jaw-Jung Shin, Burn J. Lin, “Influence of Data Volume and EPC on Process Window in Massively Parallel E-Beam Direct Write,” Proc. SPIE, vol. 8680 86801C-1, doi: 10.1117/12.2010865. [19] Y. Ding, C. Chu and X. Zhou, 'An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT,' 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015, pp. 1-6. [20] D. Salomon, A Concise Introduction to Data Compression, 1st ed. London, U.K.: Springer-Verlag, 2008, ch. 1, sec. 2, pp. 41-46. [21] P. C. Lin, Y. H. Pai, Y. H. Chiu, S. Y. Fang and C. C. P. Chen, 'Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system,' 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016, pp. 285-288. [22] F. Krecinic S.-J. Lin J. J. H. Chen 'Data path development for multiple electron beam maskless lithography' Proc. SPIE vol. 7970 Apr. 2011. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77572 | - |
dc.description.abstract | 由於製程演進,超大型積體電路的最小尺寸已逼近傳統光學製程的極限。繞射的問題,在越小尺寸的製程中越嚴重,所以生產成本也節節攀升。在眾多次世代製程系統中,電子束曝光因具有高解析度、無光罩和高性價比的特性,是製程的明日之星。
不過,要向多電子束曝光系統快速傳輸大量電路資料為一難解的瓶頸反應。例如要生產一個300mm的晶圓,假設要達到70WPH的生產速度,所傳輸到多電子束系統的資料速率將達到驚人的144Tb/s。所以本篇論文提出電路單元壓縮方案。我們在不同電路階層下尋找高重複性電路,藉此把它們做成壓縮單元,以供此方案的解碼器多次重複呼叫,來達成平行解壓縮運算和快速傳輸巨量資料。此外,我們也找出最佳的電路佈局切片來維持電路單元的完整,而良好的切割會加快解壓縮的過程。本論文中,我們用此方法壓縮一個電力線通訊晶片,是實驗室設計的類比電路。這個晶片大小約為2.66mm X 2.58mm,並使用TSMC 90製程製造。最後我們得出整體壓縮比可達10000倍,而解壓縮時間在電路布局區域與LineDiff Entropy [1] 相仿。一般情況下,我們更可預期電路單元壓縮方案是比LineDiff Entropy [1]快的。 因此方案概念簡單且有效率,它可以用在運算資源有限的系統中。最後我們的結果顯示,此方案可達到超高壓縮比和快速解壓縮,所以很適合多電子束曝光系統。 | zh_TW |
dc.description.abstract | With the advance of technology, the feature size of Integrated Circuits(IC) are shrinking to the limit of conventional optical lithography systems. Diffraction has been a severe obstacle for cost-effective production. Among next-generation lithography systems, electron beam lithography has high potential due to its high resolution, maskless and cost-effective features.
However, the transmission of enormous layout data to e-beam lithography systems becomes a bottleneck of the systems. For instance, if we want to produce a 300-mm wafer under the requirement of 70 WPH, the data rate between a data center and multiple e-beam machines will reach 144Tb/s. Therefore, the thesis presents a new lossless layout compression and decompression algorithm called Cell-based Compression Scheme. The scheme is designed for transferring high volume data and parallel decompression. It finds out cells that have high repetitiveness at different circuit hierarchies. Then, the algorithm compresses these cells as compression units. Afterwards, the decoder of the scheme decodes massive layout data by frequently calling these compression units. Besides, we figure out the best stripe size for the intactness of cells, which will speed up the decoding process. In the thesis, we utilize Cell-based method to compress a powerline communication chip which is an analog circuit and is designed by our lab. The chip is 2.66mm X 2.58mm in size and is fabricated under TSMC 90. Last, we conclude that the compression ratio reaches 10000x and the decoding time as fast as LineDiff Entropy [1] in layout covered regions. In general case, we can expect Cell-based method is faster than LineDiff Entropy in decoding. Because the algorithm is simple and effective, the decoder of Cell-based Compression Scheme can be implemented with limited computing resources. The benchmark shows it has really high compression ratio and is capable of fast decoding. | en |
dc.description.provenance | Made available in DSpace on 2021-07-10T22:09:26Z (GMT). No. of bitstreams: 1 ntu-107-R03943130-1.pdf: 5227346 bytes, checksum: 611757638630e8f60aa9ab5206459825 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES ix LIST OF TABLES xiii Chapter 1 Introduction 1 1.1 Motivation and Contribution 2 1.2 Organizations 3 Chapter 2 Preliminaries 5 2.1 Maskless lithography 5 2.1.1 Electron-beam Lithography 6 2.1.2 Parallelism 8 2.1.3 Performance and Bottleneck 12 2.2 Compression Scheme for E-beam Lithography System 13 2.3 Compression Algorithms 15 2.3.1 Lempel-Ziv [4] 15 2.3.2 Block Context Copy Combinatorial Coding (BC4) [5] 17 2.3.3 LineDiff Entropy [1] 19 2.4 Basic Knowledge 22 2.4.1 2D Rotation Matrix [10] 22 2.4.2 Pixel Specs in Computer Graphics [10] 23 2.4.3 Non-zero Winding Rule [10] 24 2.4.4 Even Odd Rule [10] 25 2.4.5 Weiler–Atherton Clipping Algorithm [11] 26 Chapter 3 Methodology 29 3.1 Cell-based Compression Scheme 29 3.2 Layout Data Extraction 32 3.2.1 GDSII txt Format [12] 32 3.2.2 Cell Classifier 34 3.2.3 Cell data extraction 35 3.3 Layout Construction 36 3.4 Cell Counter 40 3.4.1 Hierarchy 40 3.4.2 Counting Cells at Different Levels 41 3.5 Pixel Estimation 43 3.5.1 The Amount of Pixels of a Cell 43 3.5.2 The Compression Efficiency of A Cell 45 3.6 Cell Status Determination 46 3.6.1 Cell-dependent Boundary 47 3.6.2 Reference Location 47 3.6.3 Cell Transformation Status 48 3.6.4 Cell Status Data Structure 49 3.7 Coverage Process 49 3.7.1 Cell Residue 49 3.7.2 Coverage 50 3.7.3 Conclusion 52 3.8 Segmentation Estimation 52 3.8.1 Cut Load 53 3.8.2 Segmentation Estimator 54 3.8.3 Conclusion 56 3.8.4 Segmentation Strategy 57 3.9 Dummy Extractor and Dummy Analyzer 58 3.9.1 Dummy extractor 58 3.9.2 Dummy analyzer 59 3.10 Segmentation 61 3.11 Rasterization 63 3.11.1 Characteristics of The Floorplan 64 3.12 Encoder 68 3.12.1 The Architecture of The Encoder 68 3.12.2 LineDiff Encoder Revisit 69 3.12.3 Geometric LineDiff Encoder 71 3.12.4 Reference Code 73 3.12.5 Read Information 74 3.13 Decoder 75 3.13.1 Decoder Architecture 75 3.13.2 Geometric LineDiff Decoder 76 3.13.3 Unfinished Table 78 Chapter 4 Experiment Results 81 4.1 Results of estimation stage 81 4.1.1 Spec of the chip 81 4.1.2 Results of Layout Data Extraction 83 4.1.3 Compression Efficiency from Cell Pixel Estimation 84 4.1.4 Results of Segmentation Estimation 86 4.1.5 Results of Rasterization 90 4.1.6 Results of Dummy Analyzer 93 4.1.7 Encoder Performance 93 4.1.8 Decoder Performance 97 4.2 Analysis of The Results 98 4.2.1 Compression Ratio Analysis 98 4.2.2 Decompression Rate Analysis 99 Chapter 5 Conclusion 103 5.1 Conclusion 103 5.2 Future work 103 5.2.1 Optimization 103 5.2.2 Compression Ratio Aware Design Flow 105 5.2.3 Implementation Concept 106 REFERENCE 107 | |
dc.language.iso | en | |
dc.title | 應用於多電子束直寫系統之無損電路單元壓縮方案 | zh_TW |
dc.title | Lossless Cell-based Compression Scheme for Multiple E-Beam Direct Write Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江蕙如(Hui-Ru Jiang),蔡坤諭(Kuen-Yu Tsai),方劭云(Shao-Yun Fang) | |
dc.subject.keyword | 蝕刻,電子束,資料壓縮演算法,實體設計,光柵化,電路圖檔, | zh_TW |
dc.subject.keyword | Lithography,Electron Beam,Data Compression Algorithm,Physical Design,Rasterization,gdsII, | en |
dc.relation.page | 109 | |
dc.identifier.doi | 10.6342/NTU201802548 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2018-08-06 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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