90奈米CMOS高鏡像抑制頻率轉換器及40奈米LDMOS微型化功率放大器之研製

Abstract

本篇論文主要的目的是設計擁有148%/117% IF比例頻寬的Ka頻段免校正高鏡像抑制升頻/降頻混頻器以及40奈米橫向擴散金屬氧化物半導體(LDMOS)微型化功率放大器。 第二和第三章是兩顆分別設計於90奈米CMOS製程的Ka頻段免校正高鏡像抑制升頻/降頻混頻器。為了涵蓋衛星調變解調器(modem)其寬的操作頻率 (0.95-2.15 GHz)，在IF端使用三階城堡形狀(castle-wall)的多相濾波器(polyphase filter)使振幅和相位的誤差最小化。為了本地震盪源(LO)正交信號的產生(quadrature generation)則是使用包含兩個寬邊90度耦合器(broadside 90° coupler)和一個馬遜巴倫(Marchand balun)的四路正交分波器(four-way quadrature divider)。在不用校正情況下，單邊帶(single-sideband)升頻混頻器和鏡像抑制(image-rejection)降頻混頻器，在IF頻率展示寬的鏡像抑制比頻寬(鏡像抑制比<-30 dBc)，分別從0.6到4 GHz (148% IF比例頻寬) 和0.65到2.5 GHz (117% IF比例頻寬)。此外，單邊帶升頻混頻器和鏡像抑制降頻混頻器的RF頻寬(鏡像抑制比<-30 dBc)分別是27.7到33.3 GHz (18.36% RF比例頻寬)和17.1到20.6 GHz (18.5% RF比例頻寬)。這些鏡像抑制比特性能強韌地對抗(robust against)製程、電壓和溫度的變異以及蒙特卡羅模擬。 第四章是一個製作於40奈米製程的微型化、全積體化的2.5-GHz LDMOS功率放大器。由於高崩潰電壓的特性，LDMOS相較於現代標準的CMOS電晶體能提供優異的高功率密度。而電容性中和技術則被採用去改善LDMOS電晶體的穩定度以及提升最大可用增益。為了低成本微型化，變壓器被使用在我們提出的電路中，實現有效的功率結合和阻抗轉換。這個LDMOS功率放大器在2.5 GHz達到26.7 dBm的飽和輸出功率和24.24 dBm的1dB壓縮點輸出功率。在最近發表的CMOS功率放大器中，這個功率放大器在2.5 GHz展示最高的飽和輸出功率的功率密度1467mW/mm2而其緊密晶片面積是0.318 mm2。

The main purpose of this dissertation is to design the Ka-band calibration-free high image-rejection up/down mixers with 148%/117% fractional IF bandwidths and a 40-nm laterally diffused metal oxide semiconductor (LDMOS) miniature power amplifier (PA). In chapters 2 and 3, two Ka-band calibration-free high image-rejection up/down mixers are designed in 90-nm CMOS process. To cover the wide operating frequencies of the satellite modem (0.95-2.15 GHz), a 3-stage castle-wall polyphase filter (PPF) is used at the IF port to minimize the amplitude and phase errors. For local oscillator (LO) quadrature generation, a four-way quadrature divider composed of two broadside 90° couplers and one Marchand balun is used. The single-sideband (SSB) up mixer and image-rejection (IR) down mixer demonstrate broad IRR bandwidths at the IF frequencies (IRR<-30 dBc) from 0.6 to 4 GHz (148% fractional IF bandwidth) and from 0.65 to 2.5 GHz (117% fractional IF bandwidth), respectively, with no calibration. In addition, the RF bandwidths (IRR<-30 dBc) of the SSB up mixer is 27.7-33.3 GHz (18.36% fractional RF bandwidth), and the IR down mixer is 17.1-20.6 GHz (18.5% fractional RF bandwidth). The IRR performances are robust against process, voltage, and temperature (PVT) variations and Monte Carlo simulations. In chapter 4, a miniature fully-integrated 2.5-GHz LDMOS PA is implemented in 40-nm CMOS process. Due to the high breakdown voltage characteristic, LDMOS provides superior power density than modern standard CMOS transistor. The capacitive neutralization technique is adopted to improve stability of the LDMOS transistor while enhancing the maximum available gain. For low-cost miniaturization, the transformers are utilized in the proposed PA. Also, efficient power combining and impedance transformation can be realized. The LDMOS PA achieves saturated output power (Psat) of 26.7 dBm and OP1dB of 24.24 dBm at 2.5 GHz. With a compact chip size of 0.318 mm2, the PA demonstrates the highest Psat power area density (PAD) of 1467 mW/mm2 at 2.5 GHz among recently reported CMOS PAs.