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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君(I-Chun Cheng) | |
dc.contributor.author | Cheng-Che Lee | en |
dc.contributor.author | 李承哲 | zh_TW |
dc.date.accessioned | 2021-07-10T21:34:26Z | - |
dc.date.available | 2021-07-10T21:34:26Z | - |
dc.date.copyright | 2016-10-26 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-23 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76647 | - |
dc.description.abstract | 本研究成功地利用交疊結構製備較薄且絕緣能力良好的氧化鉿/氧化鋁交疊介電薄膜,並應用於可撓性p型氧化亞錫薄膜電晶體之閘極介電層,再以氮化矽作為背通道鈍化層,進一步改善氧化亞錫薄膜電晶體元件特性。並且探討機械應變對可撓性氧化亞錫薄膜電晶體電特性的影響。最後,我們研究可撓性氧化亞錫薄膜電晶體在電偏壓下的穩定性,並且探討機械應變對此特性的影響。
研究中以原子層沉積系統於200 ℃製備氧化鉿及氧化鉿/氧化鋁交疊介電薄膜。低掠角X光繞射結果顯示氧化鉿薄膜為多晶結構,而氧化鉿/氧化鋁交疊薄膜則呈現非晶結構。標準片50 nm厚氧化鉿具有良好的絕緣特性,35 nm則漏電流過大,相對地,35 nm厚氧化鉿/氧化鋁交疊薄膜具有更佳的絕緣特性,且厚度降低至22 nm同樣具有良好的絕緣能力,有利於應用可撓性氧化亞錫薄膜電晶體。接著,我們使用射頻磁控濺鍍系統製備電晶體主動層材料,製程中以金屬錫作為靶材,通入微量氧氣,搭配後退火製程以得到氧化亞錫薄膜。 可撓性氧化亞錫薄膜電晶體採倒置交錯型結構,以35 nm及22 nm氧化鉿/氧化鋁交疊薄膜作為閘極介電層所獲得之元件電特性表現與使用50 nm氧化鉿閘極介電層相當。電晶體的場效載子遷移率與臨界電壓隨著張應變量增大而下降,次臨界擺幅呈現上升趨勢,在承受壓應變時,則無明顯的電性變化。相較於50 nm氧化鉿介電層,使用較薄的氧化鉿/氧化鋁交疊介電層,在機械應變影響下電晶體的特性參數變化皆較小。在閘極正偏壓穩定性測試部份,與使用50 nm氧化鉿介電層的結果相似,具氧化鉿/氧化鋁交疊閘極介電層的電晶體其正偏壓不穩定性主要來自於界面缺陷或介電層內部缺陷的電荷捕捉;但在負偏壓測試中,可能是受到氧化鋁與氧化亞錫間界面特性不佳的影響,造成次臨界擺幅隨之改變,由此可得知偏壓不穩定性來源同時包含界面缺陷的電荷捕捉及額外缺陷的產生。此外,在定偏壓穩定性測試下,相較於50 nm氧化鉿介電層,由於22 nm的氧化鉿/氧化鋁交疊薄膜所承受的電場較大,因此電晶體的臨界電壓偏移量較大,且可能因受到氧化鋁影響,負偏壓測試下,此偏移量在機械應變影響下會顯著增加,反觀正偏壓測試,使用22 nm氧化鉿/氧化鋁交疊閘極介電層的氧化亞錫薄膜電晶體其臨界電壓偏移量值在機械應變影響下則相對穩定。 | zh_TW |
dc.description.abstract | In this research, a relatively thinner HfO2/Al2O3 (AHO) multilayer with good insulating property was introduced as novel gate dielectrics for on-foil flexible p-type tin monoxide (SnO) thin-film transistors (TFTs). To improve the electrical performance of flexible SnO TFTs, back channels of TFTs were passivated with a SiNx layer. Besides, the electrical characteristics of flexible SnO TFTs under the influence of mechanical strains were evaluated. Finally, the influence of mechanical strains on the gate-bias stress stability of flexible SnO TFTs was studied.
The dielectrics, including a standard HfO2 single layer and an AHO multilayer were deposited by atomic layer deposition (ALD) at 200°C. The grazing incidence X-ray diffraction (GIXRD) patterns showed the HfO2 layer was polycrystalline while the AHO multilayer had an amorphous structure. The standard 50-nm-thick HfO2 single layer shows good insulating property, but 35-nm-thick HfO2 layer had high leakage current. The AHO multilayers with thickness of 35 nm and 22 nm relatively showed better insulating property. It was promising for the implementation of flexible SnO TFTs. The active layer, 15-nm-thick SnO thin film, was deposited by reactive rf-magetron sputtering using a metallic tin target in O2/Ar ambient at room temperature, followed by a furnace annealing at 225 | en |
dc.description.provenance | Made available in DSpace on 2021-07-10T21:34:26Z (GMT). No. of bitstreams: 1 ntu-105-R03941027-1.pdf: 8065399 bytes, checksum: 9a20c579bc1fd1e98f71f4fd2811cdf1 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 致謝 i
中文摘要 ii ABSTRACT iv 目錄 vi 圖目錄 ix 表目錄 xv 第一章 緒論 1 1.1 軟性顯示技術發展概況 1 1.2 薄膜電晶體發展背景 2 1.3 研究動機 3 1.4 論文架構 4 第二章 理論與文獻回顧 5 2.1 薄膜電晶體簡介 5 2.1.1 薄膜電晶體之元件結構 5 2.1.2 薄膜電晶體之工作原理 6 2.1.3 薄膜電晶體之特徵參數 8 2.1.4 薄膜電晶體之偏壓穩定性 11 2.2 氧化亞錫發展背景 12 2.2.1 氧化亞錫發展 12 2.2.2 氧化亞錫結構與能帶 12 2.2.3 氧化亞錫缺陷 13 2.2.4 氧化亞錫薄膜電晶體文獻回顧 15 2.3 閘極介電層介紹 32 2.3.1 漏電流密度 32 2.3.2 界面陷阱密度 33 2.3.3 介電極化效應 33 2.3.4 介電常數 35 2.3.5 高介電常數 36 2.3.6 高介電常數材料選擇 37 2.4 交疊閘極介電層 39 第三章 研究方法 43 3.1 薄膜沉積系統與原理 43 3.1.1 電漿輔助化學氣相沉積系統 (Plasma Enhanced Chemical Vapor Deposition, PECVD) 43 3.1.2 原子層沉積系統 (Atomic Layer Deposition, ALD) 44 3.1.3 電子束蒸鍍系統 (E-Beam Evapotator)[106] 45 3.1.4 射頻磁控濺鍍系統 (Radio-Frequency Magnetron Sputter) 46 3.2 微影製程與原理 47 3.3 蝕刻製程與原理 49 3.3.1 濕式蝕刻 (Wet Etching) 49 3.3.2 感應耦合電漿離子蝕刻系統 (Inductively Coupled Plasma Reactive Ion Etch, ICP-RIE) 49 3.4 氧化亞錫薄膜電晶體製程 50 3.5 MIM/MISM結構製程 57 3.6 薄膜分析儀器與原理 58 3.6.1 紫外光-可見光分光光譜儀 (UV-Visible spectrometer) 58 3.6.2 低掠角X光繞射儀 (Grazing Incident X-ray Diffraction, GIXRD) 59 3.6.3 穿透式電子顯微鏡 (Transmission Electron Microscopy, TEM) 60 3.7 電性量測儀器與原理 61 3.7.1 薄膜電晶體特性量測方法 61 3.7.2 電流-電壓量測方法 62 3.7.3 電容-電壓量測方法 62 3.7.4 彎曲測試量測法 63 第四章 實驗結果與討論 65 4.1 閘極介電層薄膜性質分析 65 4.1.1 結構分析 65 4.1.2 結晶相分析 66 4.2 閘極介電層電特性分析 67 4.2.1 漏電流密度 67 4.2.2 電容-電壓特性分析 70 4.3 氧化亞錫薄膜結晶相分析 74 4.4 氧化亞錫薄膜電晶體元件特性分析 75 4.5 可撓性氧化亞錫薄膜電晶體元件特性分析 77 4.6 以氮化矽作為背通道鈍化層之元件特性分析 79 4.7 可撓性氧化亞錫薄膜電晶體彎曲下之元件特性分析 83 4.8 可撓性氧化亞錫薄膜電晶體偏壓穩定性分析 87 4.9 可撓性氧化亞錫薄膜電晶體彎曲下之偏壓穩定性分析 96 第五章 結論與未來展望 102 5.1 結論 102 5.2 未來展望 104 附錄I 氧化亞錫薄膜電晶體偏壓穩定性比較 105 附錄II 背封裝鈍化層對可撓性氧化亞錫薄膜電晶體彎曲下元件特性影響 107 參考文獻 113 | |
dc.language.iso | zh-TW | |
dc.title | 氧化鉿/氧化鋁交疊介電層應用於可撓性P型氧化亞錫薄膜電晶體之研究 | zh_TW |
dc.title | HfO2/Al2O3 Multilayer Gate Dielectrics for Flexible P-Type SnO Thin-Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡豐羽(Feng-Yu Tsai),吳志毅(Chih-I Wu),陳建彰(Jian-Zhang Chen),吳育任(Yuh-Renn Wu) | |
dc.subject.keyword | 可撓性電子元件,p型氧化物半導體,薄膜電晶體,氧化亞錫,交疊介電層,彎曲測試,偏壓穩定性, | zh_TW |
dc.subject.keyword | flexible electronics,p-type oxide-based semiconductor,thin-film transistor (TFT),tin monoxide (SnO),multilayered dielectric,bending test,gate-bias stress stability, | en |
dc.relation.page | 120 | |
dc.identifier.doi | 10.6342/NTU201603542 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-08-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
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