原子層成長氧化層/砷化鎵之介面特性研究

Abstract

Due to the relatively high electron mobility, GaAs and InGaAs are the leading candidates as n-channel materials in post-Si generation. In0.53Ga0.47As inversion channel n-MOSFETs have been demonstrated promising device performance using atomic-layer-deposited (ALD) high-k dielectrics. [1] However, a lattice constant of 5.87Å of In0.53Ga0.47As is difficult to be integrated onto the platform a Si(001) wafer. Instead, GaAs, with a lattice constant of 5.65Å, is about half of the lattice mismatch between In0.53Ga0.47As and Si. Owing to the advantages mentioned above, GaAs and low-In content InGaAs metal-oxide- semiconductor (MOS) capacitors have been intensively studied, aiming for developing high speed and low power devices. Besides, with excellent uniformity and conformal coverage in nanometer thick film growth, atomic layer deposition (ALD) has been widely employed in depositing high-k dielectrics for MOSFETs since the 45 nm node. Therefore, as an urgent issue, intensive efforts in ALD high-k dielectrics on GaAs(001) have been carried out to characterize and perfect these interfaces. Frequency dispersion (FD) is an important index for characterizing oxide-semiconductor interfaces. ALD-oxides on GaAs usually give a large FD in capacitance-voltage (CV) curves of the MOS capacitors (MOSCAPs), particularly on n-GaAs. [2,3] Research efforts have been carried out to explain the origin of the large FD in oxides/(In)GaAs interfaces. A model assuming an exponentially decaying spatial distribution of traps from the oxide/semiconductor interface into the bulk oxide layer explained the large FD of CVs at accumulation by the interfacial traps. [4] However, this model failed to explain the dispersion in the low frequency range and the temperature-dependent dispersion. Later, a distributed border trap model based on tunneling mechanism between the oxide/semiconductor interface and the trap states in gate dielectric accounted for the large FD of CVs and conductance (GV) at accumulation. [5] Also, Chen et al combined these two models to fit the CV and GV characteristics in depletion region to inversion region. [6] However, most reported high-k/III-V systems yielded high trap densities up to 1013 eV-1cm-2 as well as undesired interfacial native oxides, such that the corresponding analyses on capacitance-frequency (CF) characteristics lead to unconvincing results. [7,8] The very few high-k/GaAs(001) hetero-structures reported with low interfacial trap densities (Dit’s) are ultra-high vacuum (UHV) e-beam evaporated Ga2O3(Gd2O3) and ALD-Y2O3 on GaAs(001). [9] In the thesis, Al2O3 and Y2O3 were atomic-layer-deposited (ALD) on molecular beam epitaxy grown GaAs-(4×6). Oxide capacitance was carefully extracted by consider the accumulation layer thickness in GaAs. The oxide/semiconductor interface were characterized using CV characteristic, CF characteristic, QSCV measurement and conductance method. The CF analyses are in agreement with the conclusions given by QSCV and GV measurements for both hetero-structures. Both systems exhibit similar border trap densities, but greatly different Dit’s. Moreover, the Dit spectrum without mid gap peak is observed in Y2O3/GaAs samples. Showing low density of states below 1012cm-2eV-1, Y2O3/GaAs hetero-structure is promising for achieving inversion channel MOSFET with subthreshold swing under 75mV/dec. Another important issue discussed in the thesis is the temperature dependence frequency dispersion. After the simulation, the observed temperature dependence of frequency dispersion pointed out a temperature dependent barrier height, which is further confirmed by J-E characteristic. We concluded that the barrier height is temperature dependent, and should be extracted by electrical measurement. Moreover, the commonly observed temperature dependent frequency dispersion result from the temperature dependent barrier height (tunneling attenuation coefficient). Thus, the border trap density should be plotted with the right barrier height.