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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76533
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dc.contributor.advisor江蕙如(Iris Hui-Ru Jiang)
dc.contributor.authorYu-Cheng Linen
dc.contributor.author林禹丞zh_TW
dc.date.accessioned2021-07-09T15:53:55Z-
dc.date.available2025-10-15
dc.date.copyright2020-10-20
dc.date.issued2020
dc.date.submitted2020-10-14
dc.identifier.citation[1] GNU Linear Programming Kit, Version 4.65, http://www.gnu.org/software/glpk/glpk.html.
[2] TAU Contest 2019, https://sites.google.com/view/tau-contest-2019.
[3] K. Chang et al., 'Power benefit study of monolithic 3D IC at the 7nm technology node,' in Proc. 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 201{206, July 2015.
[4] T. H. Cormen et al., Introduction to Algorithms. MIT Press, 2009.
[5] G. B. Dantzig, Linear Programming and Extensions. Princeton University Press, 1963.
[6] W. C. Elmore, 'The transient response of damped linear network with particular regard to wideband amplifiers,' Journal of Applied Physics, vol. 19, no. 1, pp. 55-63, Jan. 1948.
[7] K. Fischer et al., 'Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing,' in Proc. 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), pp. 5-8, May 2015.
[8] D. Hyun and Y. Shin, 'Integrated approach of airgap insertion for circuit timing optimization,' ACM Trans. on Des. Autom. Electron. Syst., vol. 24, no. 2, pp. 24:1-24:22, Feb. 2019.
[9] Y. Jung et al., 'Integrated airgap insertion and layer reassignment for circuit timing optimization,' in Proc. 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 32-37, January 2020.
[10] S. Natarajan et al., 'A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm 2 SRAM cell size,' in Proc. 2014 IEEE International Electron Devices Meeting, pp. 3.7.1-3.7.3, December 2014.
[11] S. Park et al., 'Air-gaps for high-performance on-chip interconnect part ii: modeling, fabrication, and characterization,' Journal of Electronic Materials, vol. 37, no. 10, pp. 1534-1546, Oct. 2008.
[12] C. Penny et al., 'Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits,' in Proc. Int. Interconnect Technology Conf., pp. 1-4, May 2017.
[13] L. Xia et al., 'Method for forming an air gap in multilevel interconnect structure,' US Patent App. 11/869,409, Oct., 2007.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76533-
dc.description.abstract氣隙是藉由在導線間的金屬導線間介電層形成空隙來降低導線電容的技術。由於氣隙的形成需要高昂的成本,因此能夠置入氣隙的繞線層(氣隙繞線層)之數量是有限制的。基於導線電容的下降,氣隙可以用來優化電路時序,但優化後不能產生任何保持時間(hold time)違例。為了在有限的氣隙繞線層中置入氣隙,有兩個問題必須被處理。分別是繞線層重新分配與氣隙置入。前者會決定每個導線片段所在的繞線層,將導線片段移至氣隙繞線層或從氣隙繞線層移走。後者會決定每個在氣隙繞線層的導線片段之氣隙置入量。在這篇論文中,我們提出了一個方法來處理這兩個問題以最小化建立時間(setup time)違反總量,同時不產生任何保持時間違例。我們提出一個以網路流為基礎的氣隙置入方法,在決定一個導線片段的氣隙置入量時會考慮部分的氣隙置入量,並能在大多數情況下對一個固定繞線層分配的連線找到氣隙置入的最佳解。實驗結果顯示我們的方法與先前的方法相比,達成稍微更多的建立時間改善僅需要約24%的執行時間。zh_TW
dc.description.abstractAirgap is a technique to reduce interconnect capacitance by forming voids in inter-metal dielectrics (IMD) between interconnects. The number of layers that can insert airgap (airgap layers) is limited because of the high cost of airgap formation. With the utilization of airgap, circuit timing can be optimized due to the reduction of interconnect capacitance. However, hold time violations are not allowed after airgap insertion. In order to insert airgap with limited airgap layers, two problems need to be addressed. They are layer reassignment and airgap insertion. The former determines the layer of each wire segment. It can move wire segments to or from airgap layers. The latter determines the amount of airgap inserted to each wire segment in airgap layers. In this thesis, we propose a method to cope with these two problems for minimizing setup total negative slack (TNS) without generating hold time violations. We propose a network flow based airgap insertion method, which considers partial airgap for inserting airgap to a wire segment and finds an optimal solution for the airgap insertion of a setup timing critical net with fixed layer assignment in most cases. Experimental results show that our method can achieve slightly more setup TNS improvement with only about 24% runtime in comparison with the method of a previous work.en
dc.description.provenanceMade available in DSpace on 2021-07-09T15:53:55Z (GMT). No. of bitstreams: 1
U0001-1410202007254000.pdf: 2732367 bytes, checksum: 489eef51353aebe26d1e4b1a3b45c2ec (MD5)
Previous issue date: 2020
en
dc.description.tableofcontentsAcknowledgements iii
Abstract (Chinese) iv
Abstract vi
List of Tables x
List of Figures xi
Chapter 1. Introduction 1
1.1 Introduction to Airgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 A Motivational Example and Related Work . . . . . . . . . . . . . . . . 2
1.3 The Major Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 2. Problem Formulation 5
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Layer Reassignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Airgap Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Timing Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3. Preliminaries 10
3.1 Graph Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 The Method of a Previous Work . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 4. Methodology 13
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Graph-based Layer Reassignment (GLR) . . . . . . . . . . . . . . . . . . 14
4.3 Network Flow Based Airgap Insertion (FAI) . . . . . . . . . . . . . . . . 15
4.4 Short Circuits Identi cation . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 5. Experimental Results 26
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 Airgap Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 6. Conclusion 32
Bibliography 33
dc.language.isoen
dc.subject氣隙zh_TW
dc.subject時序最佳化zh_TW
dc.subject繞線層重新分配zh_TW
dc.subjectairgapen
dc.subjecttiming optimizationen
dc.subjectlayer reassignmenten
dc.title氣隙置入結合繞線層重新分配於電路時序最佳化之應用zh_TW
dc.titleCircuit Timing Optimization by Airgap Insertion with Layer Reassignmenten
dc.typeThesis
dc.date.schoolyear109-1
dc.description.degree碩士
dc.contributor.oralexamcommittee張耀文(Yao-Wen Chang),李建模(James Chien-Mo Li),林忠緯(Chung-Wei Lin)
dc.subject.keyword氣隙,繞線層重新分配,時序最佳化,zh_TW
dc.subject.keywordairgap,layer reassignment,timing optimization,en
dc.relation.page34
dc.identifier.doi10.6342/NTU202004262
dc.rights.note同意授權(全球公開)
dc.date.accepted2020-10-14
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
dc.date.embargo-lift2025-10-15-
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