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Title: | 高效保證資料持續性之非揮發交易快取 Nonvolatile Transaction Cache for Efficient Persistence Guarantee |
Authors: | Chun-Hao Lai 賴君濠 |
Advisor: | 楊佳玲 |
Keyword: | 持續記憶體,非揮發記憶體,資料一致性,單元性,耐用性,持續性, Persistent memory,nonvolatile memory,data consistency,atomicity,durability,persistence, |
Publication Year : | 2016 |
Degree: | 碩士 |
Abstract: | 持續記憶體架構是為一融合傳統主記憶體以及儲存單元的的新技術。藉由可接於記憶體匯流排的非揮發隨機存取記憶體 (NVRAM) 可位元組定址能力 (byte-addressability) 以及存儲單元所需要的非揮發特性 (non-volatility),持續記憶體架構將是未來相當重要的新架構。有了持續記憶體架構的出現,將可直接將資料儲存於記憶體之中,而不用再複製到傳統硬碟或者快閃儲存系統。然而為了在記憶體階層保證資料持續性,持續記憶體必須維持資料從中央處理器快取寫到非揮發隨機存取記憶體的寫入順序。直接利用軟體指令來保證寫入順序將會造成許多中央處理器執行的限制而使得整體效能大幅下降。此外,為保證將資料寫入至記憶體的單元性,傳統軟體將會需要額外寫入一些輔助以及日誌資料。因此相關研究提出藉由硬體支援來解決上述效能下降的問題。然而,之前研究所提出的辦法並沒有完全解決此問題,而僅是將效能的負擔傳遞到快取及記憶體階層。因此,我們提出一個高效的硬體方法,提供一個新保證資料持續性的路徑,消除原本硬體架構要維持住寫入順序的負擔以及額外的日誌資料寫入,將整體效能提升至接近於原有沒有保證持續性軟體的效能。 Persistent memory is a new technique that merges main memory (DRAM) and storage (disk/flash) into one component. It can be implemented by memory-bus mounted nonvolatile memory (NVRAM), which incorporates the byte-addressability of memory and the non-volatility of storage devices. Persistent memory directly benefits computer system performance by allowing in-memory data to persist immediately without the need for accessing secondary storage, such as flash and disks. However, to ensure data persistence in memory, persistent memory systems need to preserve the ordering of writes from CPU caches toward NVRAM main memory. Directly utilizing the software instructions to ensure the write ordering will push much execution burden on CPUs and result to much performance degradation. Besides, to ensure the atomicity of storing operations to persist data, additional meta-data and logging operations are added into traditional programs without persistence guarantee. And thus, multiple hardware supported solution is proposed. However, previous hardware solutions do not solve the problem at all, which propagates the performance overhead toward cache or memory hierarchy. Therefore, we propose an efficient hardware solution and provide a new persistent path, which frees existing architecture from handling the write ordering, eliminates logging overhead and increases the overall performance near the program without persistence guarantee. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76450 |
DOI: | 10.6342/NTU201602526 |
Fulltext Rights: | 同意授權(全球公開) |
metadata.dc.date.embargo-lift: | 2021-11-02 |
Appears in Collections: | 資訊工程學系 |
Files in This Item:
File | Size | Format | |
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ntu-105-R03922024-1.pdf | 4.48 MB | Adobe PDF | View/Open |
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