請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74853
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
dc.contributor.author | Kai Wang | en |
dc.contributor.author | 王開 | zh_TW |
dc.date.accessioned | 2021-06-17T09:08:53Z | - |
dc.date.available | 2020-11-04 | |
dc.date.copyright | 2019-11-04 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-10-28 | |
dc.identifier.citation | [1] J. A. Fredenburg and M. P. Flynn, 'A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,' in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec. 2012.
[2] Z. Chen, M. Miyahara and A. Matsuzawa, 'A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC,' 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C64-C65. [3] W. Guo and N. Sun, 'A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator,' ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 405-408. [4] H. Tai, Y. Hu, H. Chen and H. Chen, '11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197. [5] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters, 2nd ed. John Wiley & Sons, Hoboken, New Jersey, 2017. [6] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl and B. Nauta, 'A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time,' 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, 2007, pp. 314-605. [7] A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, 'A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator,' 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2008, pp. 246-610. [8] M. Shim et al., 'Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC,' in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1077-1090, April 2017. [9] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. McGraw-Hill, 2002. [10] C. Liu, S. Chang, G. Huang and Y. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [11] Y. Hu, J. Lin, D. Lin, K. Lin and H. Chen, 'An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration,' 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, 2018, pp. 253-256. [12] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, 'A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1 MS/s,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [13] T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee, “Noise analysis for comparator-based circuits,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 3, pp. 541–553, Mar. 2 [14] Z. Chen, M. Miyahara and A. Matsuzawa, 'A 2ndorder fully-passive noise-shaping SAR ADC with embedded passive gain,' 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, 2016, pp. 309-312. [15] Y. Shu, L. Kuo and T. Lo, 'An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016. [16] C. Liu and M. Huang, '28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter,' 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 466-467. [17] Y. Lin, C. Tsai, S. Tsou, R. Chu and C. Lu, 'A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C234-C235. [18] W. Guo, H. Zhuang and N. Sun, 'A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C236-C237. [19] S. Li, B. Qiao, M. Gandara and N. Sun, 'A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure,' 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 234-236. [20] J. Liu, S. Li, W. Guo, G. Wen and N. Sun, 'A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT Delta Sigma ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer,' in IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 428-440, Feb. 2019. [21] Y. Lin, C. Lin, S. Tsou, C. Tsai and C. Lu, '20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET,' 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 330-332. [22] A. AlMarashli, J. Anders, J. Becker and M. Ortmanns, 'A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C240-C241. [23] A. Sanyal, K. Ragab, L. Chen, T. R. Viswanathan, S. Yan and N. Sun, 'A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping,' Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-4. [24] S. Hsieh and C. Hsieh, 'A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator,' 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 240-242. [25] S. Lee, A. P. Chandrakasan and H. Lee, 'A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC,' 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, 2011, pp. 355-358. [26] H. Liu, M. Liu and Z. Zhu, 'A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR,' 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi'an, China, 2019, pp. 1-2. [27] S. Lee, S. Park, H. Park and J. Sim, 'A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,' in IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 651-659, March 2011. [28] T. Oh, H. Venkatram and U. Moon, 'A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information,' in IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 961-971, April 2014. [29] D. Johns and K. Martin, Analog Integrated Circuit Design, New York, USA: Wiley, 1997. [30] X. Huang et al., 'Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction,' 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, Taipei, 2012, pp. 1-4. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74853 | - |
dc.description.abstract | 本論文提出了一個全新的比較器架構,以達到更佳的比較器效率,得以實現一個雜訊整形連續漸進式類比數位轉換器。
一般來說,要實現一個雜訊整形連續漸進式類比數位轉換器,要先做前幾筆殘值資料的取樣,再對取樣後的殘值做積分的動作。而在做殘值資料的取樣時,會因為電荷分享的行為而導致殘值訊號的振幅衰減。同樣的,為了減少功率消耗,本論文使用被動式殘值積分的方法,以省去使用主動積分電路所消耗的功耗,同時也節省電路的複雜度。然而,使用被動式殘值積分的方式同樣會因為電荷分享的行為而導致殘值訊號的振幅衰減。 為了補足損失掉的訊號振幅,通常會利用多輸入差動對的比較器來解決,而這種多輸入差動對的比較器,會因為架構的關係,先天上產生較多的雜訊,對高解析度的類比數位轉換器來說,產生足夠大的影響。同時,比較器中輸入殘值的差動對因為尺寸較大的關係,也會產生更大的返回雜訊,同樣對電路設計造成傷害。 本論文提出的環型比較器,可以解決上述的問題,在不用加大輸入差動對的尺寸的情況下,能彌補電荷分享造成的增益損失,也因為架構的關係,比較器在不引入更多雜訊的同時,功率消耗是跟輸入訊號相關的,使得整體功耗比傳統的比較器還低,以利於高解析、低功耗之類比數位轉換器的設計。 本文所提出的類比數位轉換使用40奈米CMOS製程實現。在0.9V的供電下,所消耗的功耗是14.8微瓦,量測的最高頻寬內的信號與雜訊失真比為75dB,等效為170.3dB的Schreier 效能指標。 | zh_TW |
dc.description.abstract | This thesis proposes a brand new comparator architecture which improves the ratio between power consumption and input-referred noise, and is combined with a noise-shaping successive-approximation-register analog-to-digital converter (NS-SAR ADC).
To implement a NS-SAR ADC, we need to do the residue sampling first, then the residue voltage will be integrated. Usually, it will generate a gain loss during the passive residue sampling which is done by charge sharing. This gain loss causes the amplitude degeneration of the residue voltage. Besides, in order to reduce power consumption, the passive integration is adopted in this work to avoid the power-hungry active circuit, and reduce the complexity of circuit at the same time. However, the passive integration will also cause degeneration of the residue voltage since the passive integration is also done by charge sharing. In order to compensate the degeneration of the signal amplitude, multiple-input-pair comparator is often adopted to solve the issue. However, the conventional multiple-input-pair comparator induces more thermal noise than the single-input-pair one does. Thus, the noise shaping SAR faces a tradeoff between noise reduction due to noise shaping and noise increase due to the use of a multiple-input-pair comparator. And the conventional NS-SAR need to consume more power on comparator to reach lower noise level. This thesis proposes a multiple-input ring comparator with a 4x passive gain to combine with the NS-SAR ADC. It not only has the input-dependent power dissipation, but also gets four times gain amplification of the NS residue voltage to compensate the loss of charge sharing while inducing less thermal noise. It’s useful in the design of low-power, and high-resolution ADC. Fabricated in 40 nm CMOS technology, the proposed NS-SAR ADC consumes 14.8μW under a 0.9-V supply, and the measured peak SNDR is 75.81-dB. Finally, the Schreier FOM is 170.3-dB for a 42kHz bandwidth at 1MS/s. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T09:08:53Z (GMT). No. of bitstreams: 1 ntu-108-R06943027-1.pdf: 4000314 bytes, checksum: b4b45509786441a90e7cb2a6983f7060 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 The Fundamentals of Analog-to-Digital Converter 4 2.1 Introduction 4 2.2 Nyquist Theorem 4 2.3 Resolution 5 2.4 Basic Error 6 2.4.1 Offset Error 6 2.4.2 Gain Error 7 2.4.3 Quantization Error 7 2.5 Basic ADC Architecture 9 2.5.1 Successive Approximation Register ADC (SAR ADC) 10 2.5.2 Discrete-Time Delta-Sigma ADC 11 2.5.3 Continuous-Time Delta-Sigma ADC 14 Chapter 3 Overview of High Resolution SAR ADC Design 16 3.1 Introduction 16 3.2 Capacitive Digital-to-Analog Converter 16 3.2.1 kT/C noise 16 3.2.2 Capacitor Mismatch 17 3.2.3 Parasitic Capacitance 19 3.3 Comparator 20 3.3.1 Voltage-Domain Comparator 20 3.3.2 Time-Domain Comparator 25 3.3.3 VCO-Based Comparator 28 3.4 Hybrid Architecture 30 3.4.1 Noise-Shaping Technique 31 3.4.2 Integrating Conversion 33 3.4.3 Time-Domain Quantization 34 3.4.4 Amplifier-Based FIR-IIR Filter 35 Chapter 4 A 15-bit Low-Power Noise-Shaping SAR ADC with a 4x Passive Gain Multiple-Input Ring Comparator 37 4.1 Introduction 37 4.2 Proposed Architecture 38 4.3 Noise-Shaping Analysis 43 4.3.1 Residue Sampling 43 4.3.2 Residue Integration 44 4.3.3 Noise Transfer Function (NTF) 46 4.4 Circuit Implementation 52 4.4.1 Capacitive-DAC Switching and Power-saving Technique 53 4.4.2 4x Passive Gain Multiple-Input Ring Comparator 55 4.4.3 Amplifier 62 4.4.4 Bootstrap Switch 63 4.4.5 Clock Generator 64 4.4.6 Frequency Eliminator 65 Chapter 5 Experiments Results 67 5.1 Environment Setup 67 5.2 Layout Design 68 5.3 PCB Design 69 5.4 Measurement Results 70 Chapter 6 Conclusions and Future Work 77 6.1 Conclusions 77 6.2 Future Work 77 REFERENCE 79 | |
dc.language.iso | en | |
dc.title | 一個具有四倍增益的多輸入環形比較器的高解析度且低功耗之雜訊整形連續漸進式類比至數位轉換器 | zh_TW |
dc.title | A 74.6dB SNDR Low-Power Noise-Shaping SAR ADC With a 4x Passive Gain Multiple-Input Ring Comparator | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鍾勇輝(Yung-Hui Chung),郭建宏(Chien-Hung Kuo) | |
dc.subject.keyword | 雜訊整形,連續漸進式數位至類比轉換器,數位至類比轉換器,環形比較器, | zh_TW |
dc.subject.keyword | Noise-shaping,successive-approximation-register analog-to-digital converter (SAR ADC),digital-to-analog converter (DAC),Ring comparator, | en |
dc.relation.page | 82 | |
dc.identifier.doi | 10.6342/NTU201904243 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-10-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-108-1.pdf 目前未授權公開取用 | 3.91 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。