請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74803完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Tzyy-Shyang Tang | en |
| dc.contributor.author | 唐梓翔 | zh_TW |
| dc.date.accessioned | 2021-06-17T09:07:52Z | - |
| dc.date.available | 2021-12-02 | |
| dc.date.copyright | 2019-12-02 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-11-26 | |
| dc.identifier.citation | [1] Y. S. Hu, et al, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS,”in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 81-84, Nov. 2014.
[2] C.-C. Liu et al., ”A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010 [3] P.-C. Huang, et al., “An 8-bit 900MS/s Two-Step SAR ADC,” in IEEE Int. Symp. Circuits and Systems, pp. 2898-2898, May. 2016. [4] F. Kuttner, 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS,' in IEEE ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002. [5] H.-Y. Tai, et al., “A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 196-197, Feb. 2014. [6] G. Huang, S. Chang, C. Liu and Y. Lin, 'A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,' IEEE Journal of Solid-State Circuits, pp. 2783-2795, Nov. 2012. [7] H. Wei, P. Zhang, B. D. Sahoo and B. Razavi, 'An 8 Bit 4 GS/s 120 mW CMOS ADC,' IEEE Journal of Solid-State Circuits, pp. 1751-1761, Aug. 2014. [8] M. El-Chammas and B. Murmann, 'A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,' IEEE Journal of Solid-State Circuits, pp. 838-847, April 2011. [9] S. Lee, A. P. Chandrakasan and H. Lee, 'A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration,' IEEE Journal of Solid-State Circuits, pp. 2846-2856, Dec. 2014. [10] C. Lin, Y. Wei and T. Lee, '27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration,' in IEEE ISSCC Dig. Tech. Papers, pp. 468-469, Feb. 2016. [11] N. Le Dortz et al., '22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS,' IEEE Journal of Solid-State Circuit, pp. 386-388, Feb. 2014. [12] D. Stepanovic and B. Nikolic, 'A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,' IEEE Journal of Solid-State Circuits, pp. 971-982, April 2013. [13] J. Song, K. Ragab, X. Tang and N. Sun, 'A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration,' IEEE Journal of Solid-State Circuits, pp. 2563-2575, Oct. 2017. [14] D. Li, Z. Zhu, R. Ding, M. Liu, Y. Yang and N. Sun, 'A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew calibration,' IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 16-20, Jan. 2019. [15] C. Wang and J. Wu, 'A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection,' in IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1102-1114, June 2009. [16] Chung-Yi Wang and Jieh-Tsorng Wu, 'A background timing-skew calibration technique for time-interleaved analog-to-digital converters,' IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 299-303, April 2006. [17] T. Miki et al., 'A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,' IEEE Journal of Solid-State Circuits, pp.1372-1381, June 2015. [18] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, 'Yield and speed optimization of a latch-type voltage sense amplifier,' IEEE Journal of Solid-State Circuits, pp. 1148-1158, July 2004. [19] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, 'A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s,' IEEE Journal of Solid-State Circuit, pp. 1007-1015, May 2010. [20] C. Liu, S. Chang, G. Huang and Y. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,' IEEE Journal of Solid-State Circuits, pp. 731-740, April 2010 [21] Shuo-Wei Mike Chen and R. W. Brodersen, 'A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS,' in IEEE ISSCC Dig. Tech. Papers, pp. 2350-2359, Feb 2006. [22] J. Mulder et al., 'An 800MS/s dual-residue pipeline ADC in 40nm CMOS,'in IEEE ISSCC Dig. Tech. Papers, pp. 184-18 , Feb 2011. [23] Yuan-Ching Lien, 'A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration,' in IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 1-2, June 2016. [24] A. M. Abo, et al., “A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuit, pp. 599-606, May 1999. [25] J. Sauerbrey, D. Schmitt-Landsiedel and R. Thewes, 'A 0.5-V 1-μW successive approximation ADC,' IEEE Journal of Solid-State Circuits, pp. 1261-1265, July 2003. [26] F. Goodenough, “Analog technology of all varieties dominate ISSCC,” Electronic Design, pp. 96, Feb. 1996. [27] H. Huang, et al., “A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer,” in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 289-292, Nov. 2015. [28] L. Kull, et al., “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,” IEEE Journal of Solid-State Circuits, pp. 3049-3058, Dec. 2013. [29] Y. Chung, M. Wu and H. Li, 'A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS,' IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 10-18, Jan. 2015. [30] David K. Cheng, Field and Wave Electromagnetics,2/e, 2013. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74803 | - |
| dc.description.abstract | 在現今很多設備的應用像是無線通訊、智慧電視等等皆需要8位元到12位元每秒取樣幾億次高速取樣以及中高解析度的類比至數位轉換器，放在接收端來處理從傳送器傳來的訊號。
本論文提出了一個有時間偏移校正之十二位元每秒八億次取樣的時間交錯式取樣的連續漸進式類比至數位轉換器，以一個28奈米CMOS製程實現。架構上使用一個六位元的Coarse SAR ADC來輔助四個通道的十二位元Fine SAR ADC的方式，其中為了提高Coarse SAR ADC速度，使用電荷分配的兩階段連續漸進式類比至數位轉換器。 為了要去解決交錯式類比至數位轉換器的通道間時脈偏移不匹配造成線性度不好的問題，提出了一個時脈偏移校正的技巧，使用零交越(zero-crossing)的偵測方式搭配上Coarse ADC和Fine ADC的架構去偵測時脈偏移量，有效降低調整時脈偏移量時所造成的時脈波動(timing fluctuation)，並調整通道間時脈，達成通道間的偏移補償及校正。 本作品的量測結果顯示可操作在每秒八億的轉換及輸入頻率為4億赫茲,SNDR在Fin=20MHz以及Fin=350MHz 分別為59.63dB和49.55dB。功率消耗為4.398 毫瓦。並得到優良的品質因數(FoM)為 16.73 fJ/c.-s。其適合用在高電能效益的無線通訊與乙太網路應用中。 | zh_TW |
| dc.description.abstract | Recently, in many applications, such as wireless communication, smart TV, etc., need 8-bit to 12-bit and sampling rate hundreds MS/s to GS/s medium-to-high resolution analog-to-digital converters, which are placed at the front end of the receiver.
This thesis proposed a 12-b 800-MS/s time-interleaved SAR ADC with timing-Skew calibration in 28nm CMOS. The architecture is a 6-bit coarse ADC to assist the 12-bit four fine channel ADC to achieve time-interleaved. In order to increase the conversion speed in coarse ADC, use the two-step SAR ADC with charge sharing technique. Besides, we propose a timing-skew calibration to eliminate the skew effect between the channel. The zero-crossing algorithm is used in our timing-skew calibration and it combined with the subranging architecture so as to reduce timing fluctuation. This time-interleaved SAR ADC achieves SNDR 59.63db at the conversion of 800MS/s with 20MHz input signal and SNDR 49.55db at the conversion of 800MS/s with 350MHz input signal. It consumes 4.398mW and gets a good FoM of 16.73 fJ/conversion-step. It is suitable for energy-efficient wireless communication and an Ethernet network application. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T09:07:52Z (GMT). No. of bitstreams: 1 ntu-108-R06943039-1.pdf: 9620023 bytes, checksum: 9fc9cb9495521d3c1249393cb8f5749e (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III Contents IV List of Figures VII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Offset and Gain Error 3 2.2.2 Differential and Integral Nonlinearity (DNL and INL) 4 2.2.3 Signal-to-Noise Ratio (SNR) 4 2.2.4 Total Harmonic Distortion (THD) 5 2.2.5 Spurious-Free Dynamic Range (SFDR) 5 2.2.6 Signal to Noise and Distortion Ratio (SNDR) 6 2.2.7 Effective Number of Bits (ENOB) 6 2.2.8 Figure of Merit (FoM) 6 2.3 ADC Architectures 7 2.3.2 Successive-Approximation-Register Architecture 7 2.3.3 Flash ADC Architecture 8 2.3.4 Time-Interleaved Architecture 9 Chapter 3 Proposed Time-Interleaved SAR ADC 12 3.1 Error Sources in Time-Interleaved 12 3.1.1 Offset Mismatch 12 3.1.2 Gain Mismatch 15 3.1.3 Timing Skew Mismatch 18 3.2 Proposed Architecture 22 3.2.1 Two-Step SAR ADC Architecture 23 3.2.2 Settling-Time Relief Technique 26 3.2.3 Error Correction Technique 27 3.2.4 Detect–and–Skip Algorithm 29 3.3 Timing Skew Calibration 31 3.3.1 Prior Work Solving Timing Skew Detection Method 32 3.3.1.1 Correlation-based algorithm 32 3.3.1.2 Variance-based algorithm 35 3.3.1.3 Zero-Crossing Algorithm 36 3.3.2 Proposed Timing Skew Calibration Algorithm 40 3.3.2.2 Zero-Crossing Algorithm with Subrange Architecture 40 3.3.2.2.1 Timing Fluctuation Effect 43 3.3.2.2.2 Referencing Scheme 44 3.3.2.3 Skew Calibration Parameter Consideration 46 3.3.2.3.1 Sampling Point Selection 48 3.3.2.3.2 Step Size Selection 49 Chapter 4 Circuit Implementation 51 4.1 Introduction 51 4.2 Clock Generator 51 4.2 Bootstrapped Circuit 54 4.3 Comparator Circuit 58 4.3.1 Noise and Speed 59 4.3.2 Offset 62 4.3.3 Simulation Result 63 4.4 SAR Digital Logic 64 4.5 Capacitive DAC 66 4.6 Timing Adjustment Circuit 67 4.7 APR circuit 68 4.8 ADC Simulation Result 70 4.8.1 Post-Layout Simulation 70 4.8.1 PVT Simulation 72 4.8.2 Bond-Wire Simulation 73 4.9 Summary 74 Chapter 5 Measurement Setup and Result 75 5.1 Test Setup 75 5.1.1 Layout Introduction 76 5.1.2 PCB Design Introduction 76 5.1.3 Impedance Matching 80 5.1.3 SI/PI Simulation 81 5.2 Measurement Result 84 5.2.1 Static Performance 84 5.2.2 Dynamic Performance 84 5.2.3 Issue Discussions 87 5.2.3.1 Coarse ADC and Fine ADC Timing Mismatch in Zero-Crossing Algorithm 87 5.2.3.2 Root Cause for the Issue 93 5.2.3.2.1 Clock Line Simulation 93 5.2.3.2.2 Coarse ADC and Fine ADC Bandwidth Mismatch 94 5.2.3.2.3 Solution for the Bandwidth Mismatch 100 5.2.3 Power Dissipation 101 5.3 Summary 101 Chapter 6 Conclusion and Future Work 103 6.1 Conclusion 103 6.2 Future Work 104 Bibliography 105 | |
| dc.language.iso | en | |
| dc.subject | 類比至數位轉換器 | zh_TW |
| dc.subject | 時脈偏移校 | zh_TW |
| dc.subject | 時脈偏移不匹配 | zh_TW |
| dc.subject | 時間交錯式 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | successive-approximation register | en |
| dc.subject | time-interleaved | en |
| dc.subject | analog-to-digital converter | en |
| dc.title | 一個有時間偏移校正之十二位元每秒八億次取樣的時間交錯式連續漸進式類比至數位轉換器 | zh_TW |
| dc.title | A 12-b 800-MS/s Time-Interleaved SAR ADC
with Timing-Skew Calibration in 28nm CMOS | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鍾勇輝,胡耀升 | |
| dc.subject.keyword | 類比至數位轉換器,連續漸進式,高速,時間交錯式,時脈偏移不匹配,時脈偏移校, | zh_TW |
| dc.subject.keyword | analog-to-digital converter,time-interleaved,successive-approximation register, | en |
| dc.relation.page | 109 | |
| dc.identifier.doi | 10.6342/NTU201904316 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-11-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-108-1.pdf 未授權公開取用 | 9.39 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。