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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林坤佑(Kun-You Lin) | |
dc.contributor.author | Min-Shian Yang | en |
dc.contributor.author | 楊旻憲 | zh_TW |
dc.date.accessioned | 2021-06-17T09:07:35Z | - |
dc.date.available | 2029-11-28 | |
dc.date.copyright | 2019-12-02 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-11-29 | |
dc.identifier.citation | Federal Communications Commission, GN Docket No. 14-177, 15 FCC Record 138A1, “Use of spectrum bands above 24 GHz for mobile radio services,” [Online].Available: https://docs.fcc.gov/public/attachments/DOC-355211A1.pdf.
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Bachtold, “Ultracompact reflective-type phase shifter MMIC at C-band with 360 degree phase-control range for smart antenna combining,” IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 481-486, April 2002. [11] H. Zarei, C. T. Charles and D. J. Allstot, “Reflective-type phase shifters for multiple-antenna transceivers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 8, pp. 1647-1656, Aug. 2007. [12] M.-D. Tsai and A. Natarajan, “60 GHz passive and active RF-path phase shifters in silicon,” IEEE Radio Frequency Integrated Circuits Symp. Dig., 2009, pp 223-226 [13] K. Koh and G. M. Rebeiz, “0.13-μm CMOS phase shifters for X-, Ku-, and K-Band phased arrays,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2535-2546, Nov. 2007. [14] K. Koh and G. M. Rebeiz, “An X- and Ku-band 8-element phased-array receiver in 0.18-μm SiGe BiCMOS technology,” IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1360-1371, June 2008. [15] S. Y. Kim, D. Kang, K. Koh, and G. M. Rebeiz, “An improved wideband all-pass I/Q network for millimeter-wave phase shifters,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 11, pp. 3431-3439, Nov. 2012. [16] J. Wu, J. Kao, J. Kuo, K. Kao, and K. Lin, “A 60-GHz single-ended-to-differential vector sum phase shifter in CMOS for phased-array receiver,” IEEE MTT-S Int. Microw. Symp. Dig., June 2011, pp. 1-4. [17] K. Maruhashi, H. Mizutani and K. Ohata, “Design and performance of a Ka-band monolithic phase shifter utilizing nonresonant FET switches,” IEEE Trans. Microw. Theory Techn., vol. 48, no. 8, pp. 1313-1317, Aug. 2000. [18] C. F. Campbell and S. A. Brown, “A compact 5-bit phase-shifter MMIC for K-band satellite communication systems,” IEEE Trans. Microw. Theory Techn., vol. 48, no. 12, pp. 2652-2656, Dec. 2000. [19] Y.-C. Chiang, W.-T. Li, J.-H. Tsai and T.-W. Huang, “A 60 GHz digitally controlled 4-bit phase shifter with 6-ps group delay deviation,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 1–3. [20] B.-W. Kim, G. M. Rebeiz, “Single-ended and differential Ka-band BiCMOS phased array front-ends,” IEEE Journal of Solid-State Circuit, vol. 43, no. 10, pp. 2239-2250, Oct. 2008. [21] D. Kang, J. Kim, B. Min, and G. M. Rebeiz, “Single and four-element Ka-band transmit/receive phased-array silicon RFICs with 5-bit amplitude and phase control,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3534-3543, Dec. 2009. [22] Dong-Woo Kang, Hui Dong Lee, Chung-Hwan Kim, and Songcheol Hong, “Kuband MMIC phase shifter using a parallel resonator with 0.18 m CMOS technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 1, pp. 294-301, Jan. 2006. [23] G.-S. Shin, J.-S. Kim, H.-M. Oh, S. Choi, C.-W. Byoen, J.-H. S, J.-H. Lee, and C.-Y. Kim, “Low insertion loss, compact 4-bit phase shifter in 65 nm CMOS for 5G applications,” IEEE Microwave and Wireless Components Letters, vol. 26, no. 1, pp. 37-39, Jan. 2016. [24] J. Yang and K. Yang, “Ka-band 5-bit MMIC phase shifter using InGaAs PIN switching diodes,” IEEE Micorw. Wireless Compon. Lett., vol. 21, no. 3, pp. 151-153, Mar. 2011. [25] F. Meng, K. Ma, K.-S. Yeo and S. Xu, “A 57-to-64 GHz 0.094 mm2 5-bit passive phase shifter in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, No. 5, May 2016. [26] Q. Zheng et al., “Design and performance of a wideband Ka-band 5-b MMIC phase shifter,” IEEE Microw. Wireless Compon. Lett., vol. 27, no. 5, May. 2017. [27] C. Chen, Y. Wang, Y. Lin, Y. Hsiao, Y. Wu and H. Wang, “A 36–40 GHz full 360° ultra-low phase error passive phase shifter with a novel phase compensation technique,” 2017 47th European Microwave Conference (EuMC), Nuremberg,2017, pp. 1245-1248. [28] Y.-C. Chiang, W.-T. Li, J.-H. Tsai, and T.-W. Huang, “A 60 GHz digitally controlled 4-bit phase shifter with 6-ps group delay deviation,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 1–3. [29] D. Kang, J. Kim, B. Min, and G. M. Rebeiz, “Single and four-element Ka-band transmit/receive phased-array silicon RFICs with 5-bit amplitude and phase control,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3534-3543, Dec. 2009. [30] J. Yang and K. Yang, “Ka-band 5-bit MMIC phase shifter using InGaAs PIN switching diodes,” IEEE Micorw. Wireless Compon. Lett., vol. 21, no. 3, pp. 151- 153, Mar. 2011. [31] K. Koh and G. M. Rebeiz, “0.13-μm CMOS phase shifters for X-, Ku-, and K-Band phased arrays,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2535-2546, Nov. 2007. [32] Q. Zheng et al., “Design and performance of a wideband Ka-band 5-b MMIC phase shifter,” IEEE Microw. Wireless Compon. Lett., vol. 27, no. 5, May. 2017. [33] Z. M. Tsai et al., “FET-integrated CPW and the application in filter synthesis design method on traveling-wave switch above 100 GHz,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 5, pp. 2090-2097, May. 2006. [34] K. Y. Lin, et al., “Millimeter-wave MMIC single-pole-double-throw passive HEMT switches using impedance transformation networks,” IEEE Trans. Microw. Theory Techn., vol 51, no4, pp. 1076-1085, Apr. 2003. [35] G. Slovin, M. Xu, R. Singh, T. E. Schlesinger, J. Paramesh and J. A. Bain, “Design criteria in sizing phase-change RF switches,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 11, pp. 4531-4540, Nov. 2017. [36] F. Hu and K. Mouthaan, “A 1-21 GHz, 3-bit CMOS true time delay chain with 274 ps delay for ultra-broadband phased array antennas,” 2015 45th European Microwave Conference (EuMC), Paris, 2015, pp. 1347-1350. [37] H. Hashemi, T. S. Chu, and J. Roderick, “Integrated true-time-delay-based ultrawideband array processing,” IEEE Commun. Mag., vol. 46, no. 9, pp. 162–172, Sep. 2008 [38] D.-H. Shin, I.-B. Yok, and D.-W. Kim, ”4-20- GHz GaAs true-time delay amplifier MMIC,” IEEE Microw. Wireless Compon. Lett., vol. 27, no. 12, Dec. 2017. [39] J.-C. Chien, L.-H. Lu, ”40-Gb/s High-gain distributed amplifiers with cascaded gain stages in 0.18-micron CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2715-2725, Dec. 2007. [40] J. -C. Kao, “Research on key components for microwave and millimeter-wave wideband systems,” Ph.D. Dissertation, National Taiwan University, November. 2013. [41] H.-H. Chen, “Research of millimeter-wave low-noise amplifier and E-mode and D-mode GaAs power amplifier for 5G wireless system applications,” Master Thesis,National Taiwan University, January. 2016. [42] P. -H. Chuang, “Research of V-band On-Off-Keying modulator with transformerfeedback and Q-band low noise amplifier and W-band power amplifier,” Master Thesis, National Taiwan University, November. 2018. [43] ROGERS CORPORATION, “RO4400 series Bondply data sheet: RO4450F, RO4450T, and RO4460G2 Bondply,” RO4450F datasheet. [44] Dielectric Laboratories Incorporation, “Miniature RF blocking network,” J30BJBA012LX4 datasheet. [45] Texas Instruments, “LM317 3-terminal adjustable regulator,” low-dropout regulator datasheet. [46] Far Field (Fraunhofer) Region., [Online]. Available: http://www.antennatheory.com/basics/fieldRegions.php | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74787 | - |
dc.description.abstract | 本論文主要分為三個部分,第一部分為毫米波四位元相移器,第二個部分為毫米波真實時間延遲(True time delay)放大器,及最後一個部分的毫米波相位陣列系統(Phased array system)。
第一部分是開關式相移器的研究。相移器為相位陣列系統的關鍵元件,本論文中,一樣使用0.15 微米的增強式砷化鎵假晶高速電子移動率電晶體製程並設計了一個4 位元的開關式相移器。此相移器藉由切換低通濾波器來達到相位移的效果,其特色為低相位移誤差及極小的布局面積。另外,亦製作了各級的測試電路來驗證模擬與量測的特性,並基於量測的結果來除錯及製作改良的版本,最終得到了不錯的結果。此外,為了方便系統整合,亦驗證了只有正偏壓(0.75 V)的量測結果。 第二部分是有關毫米波真實時間延遲放大器的研究。本論文使用了 0.15 微米的增強式(Enhancement mode)砷化鎵(GaAs)假晶高速電子移動率電晶體(pHEMT)製程設計了一個有效結合開關式電容與分佈式放大器(Distributed amplifier)的人造傳輸線(Artificial transmission line)來實現調整真實時間延遲的放大器。其優點保留 了分佈式架構的寬頻特性,在28GHz 至38GHz 能有2 到3.4 dB 的寬頻增益,並提供了最大2 皮秒(picosecond)的真實時間延遲。 第三部分則是應用於38GHz 的相位陣列系統,其關鍵元件皆由0.15 微的砷化鎵假晶高速電子移動率電晶體製程製作,並整合於印刷電路板(Printed circuit board)上。此相位陣列系統的相移機制便由第二部分所製作的相移器來實現。除了相位陣列之外,亦製作了各電路的測試板,藉此驗證各電路經由打線(Bonding wire)接合後的特性。為了方便控制相位陣列,亦設計了一個可以藉由現場可程式化邏輯閘陣列(Field Programmable Gate Array)實現的數位電路,此控制電路擁有極佳彈性與擴充,可針對不同陣列數的相位陣列系統進行修改。此論文將討論相位陣列系統的整合規劃,從板材層數設計、關鍵元件腳位的布局與繞線、鏈路預算、測試板設計、數位控制電路設計及量測規劃。 | zh_TW |
dc.description.abstract | This thesis consists of three main parts, the first part is design of a 38 GHz switch type phase shifter, the second is a wideband true time delay amplifier, and the third part is the integration of a phased array system for 38 GHz.
In the first part, some preparatory work is presented. According to the preparatory work, a 38 GHz 4-bit switch type phase shifter with compact layout area is presented. The phase shifter is implemented in 0.15 micron E-mode GaAs pHEMT. It achieves 6.47° RMS phase error, 1.21 dB RMS amplitude error, and 9.95 dB average insertion loss at 38 GHz. In the second part, a wideband true time delay amplifier is designed. The TTDA is fabricated in 0.15 micron E-mode GaAs pHEMT. This TTDA applied the topology of distributed amplifier to achieve wideband operation and switching capacitor to achieve tunable time delay. Its operation bandwidth can cover 28 GHz to 38 GHz. The average gain of the TTDA is 2.75 dB to 3.25 dB. The maximum true time delay is 2 ps at 38 GHz and the maximum phase shift is 27° at 38 GHz. In the third part, integration of a 38 GHz phased array front-end is design and presented. All of the circuits are fabricated in 0.15 micron E-mode GaAs pHEMT and are packaged in PCBs. The phase shifter of the phased array front-end is the phase shifter presented in chapter 2. All of the design process and system consideration including bondwire effect, link budget, and layout consideration, are demonstrated in this chapter. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T09:07:35Z (GMT). No. of bitstreams: 1 ntu-108-R05942086-1.pdf: 18165504 bytes, checksum: cc7363a5dfc30672aafb76788792a9b2 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員會審定書 ...........................................................................................................#
誌謝 ................................................................................................................................... i 中文摘要......................................................................................................................... iv ABSTRACT ......................................................................................................................v CONTENTS .................................................................................................................... vi LIST OF FIGURES ...........................................................................................................x LIST OF TABLES ......................................................................................................... xix Chapter 1 Introduction ..............................................................................................1 1.1 Background and Motivation ...........................................................................1 1.2 Overview of Phased Array Systems ...............................................................1 1.2.1 Fundamental theory of phased array systems .......................................1 1.2.2 Architectures of phased array systems [4] ............................................3 1.3 Literature Survey ............................................................................................6 1.4 Contribution ..................................................................................................10 1.5 Thesis Organization ......................................................................................11 Chapter 2 A 38 GHz Miniaturized Switch Type Phase Shifter for Phased Array System .....................................................................................................12 2.1 Introduction...................................................................................................12 2.1.1 Motivation ...........................................................................................12 2.1.2 Fundamental theory of switching type phase Shifter ..........................13 2.2 Preparatory Works ........................................................................................15 2.2.1 Motivation ...........................................................................................15 2.2.2 Design and layout................................................................................15 2.2.3 Measurement results............................................................................17 2.2.4 Conclusion...........................................................................................24 2.3 Design and Implementation of Switch Type Phase Shifter ..........................24 2.3.1 Comparison of E-mode and D-mode pHMET switch.........................24 2.3.2 STPS design for 22.5、45、90 bits....................................................28 2.3.3 Design of 180° bit ..............................................................................32 2.4 Simulation Results of Single Bit...................................................................33 2.4.1 22.5° bit ..............................................................................................33 2.4.2 45° bit .................................................................................................34 2.4.3 90° bit .................................................................................................35 2.4.4 180° bit ...............................................................................................36 2.5 4 Bit Phase Shifter ........................................................................................37 2.5.1 Bit order consideration ........................................................................37 2.5.2 Complete schematic ............................................................................38 2.5.3 Simulation result .................................................................................39 2.6 Measurement Results....................................................................................41 2.6.1 Measurement results of test circuits ....................................................41 2.6.2 Measurement results of the 4-bit phase shifter....................................45 2.6.3 Measurement results with one-voltage supply ....................................49 2.6.4 Summary .............................................................................................51 Chapter 3 Design of a Ka-band True-Time Delay Amplifier ...............................52 3.1 Introduction...................................................................................................52 3.2 Circuit Design ...............................................................................................53 3.2.1 Circuit architecture [39][40] ...............................................................53 3.2.2 Design of the distributed amplifier .....................................................55 3.2.3 Design of the delay cell .......................................................................61 3.3 Bias Consideration and Final Layouts ..........................................................62 3.3.1 Termination resistor and blocking capacitor .......................................62 3.3.2 RF Choke ............................................................................................64 3.3.3 Bypass design ......................................................................................65 3.4 Complete Schematic and Final layouts.........................................................68 3.5 Simulation Results ........................................................................................70 3.5.1 S-parameters........................................................................................70 3.5.2 Large Signal Simulation......................................................................74 3.5.3 Stability check .....................................................................................78 3.6 Measurement Results....................................................................................83 3.7 Discussion.....................................................................................................88 3.8 Summary.......................................................................................................92 Chapter 4 Integration of A 38GHz Phased Array System....................................93 4.1 Introduction...................................................................................................93 4.2 System Plan ..................................................................................................94 4.2.1 System Block ......................................................................................94 4.2.2 Summary of system PA .......................................................................95 4.2.3 Summary of system LNA....................................................................96 4.2.4 Summary of the 38GHz 4-bit phase shifter.........................................97 4.2.5 Summary of the 38 GHz 4-element antenna array..............................98 4.2.6 PCB structure ......................................................................................99 4.2.7 Transmission line on PCB.................................................................100 4.3 PCB Layout and Extra Consideration.........................................................103 4.3.1 Off-Chip bypass ................................................................................103 4.3.2 Chip socket ........................................................................................104 4.3.3 Layout of the phased array front-end ................................................107 4.3.4 Test circuits .......................................................................................108 4.3.5 System power supply ........................................................................109 4.4 Phased Array System ..................................................................................113 4.4.1 The Phased Array states and incident angle of the Wave..................113 4.4.2 Phased array control system design ..................................................115 4.4.3 Link budget .......................................................................................121 4.5 Measurement Result ...................................................................................125 4.5.1 Measurement of test circuits .............................................................125 4.5.2 Measurement of the transmitter and receiver ....................................135 4.5.3 Measurement of the phased array front-end......................................144 4.6 Discussion...................................................................................................150 4.7 Summary.....................................................................................................154 Chapter 5 Conclusion ............................................................................................155 REFERENCE ................................................................................................................157 | |
dc.language.iso | en | |
dc.title | 應用於第五世代通訊系統之相位陣列關鍵元件與相位陣列之研究 | zh_TW |
dc.title | Research on Key Components in Phased Array Systems and Phased Array System for The Fifth Generation Communication Using GaAs pHEMT Process | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡政翰(Jeng-Han Tsai),張鴻埜(Hong-Yeh Chang) | |
dc.subject.keyword | 砷化鎵,假晶高速電子移動率電晶體,分佈式放大器,相移器,相位陣列系統,多層印刷電路板, | zh_TW |
dc.subject.keyword | Distributed amplifier,E-mode,GaAs,multi-layer PCB,pHEMT,phase shifter,phased array,switch,TRL calibration,test-kit,true time delay, | en |
dc.relation.page | 162 | |
dc.identifier.doi | 10.6342/NTU201904339 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-11-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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