請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74663完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李峻霣 | |
| dc.contributor.author | Li-Yun Liu | en |
| dc.contributor.author | 劉立耘 | zh_TW |
| dc.date.accessioned | 2021-06-17T09:05:45Z | - |
| dc.date.available | 2020-01-16 | |
| dc.date.copyright | 2020-01-16 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-01-15 | |
| dc.identifier.citation | [1] Jeff Desjardins, “Visualizing Moore’s Law in Action (1971-2019),” available at: www.visualcapitalist.com/visualizing-moores-law-in-action-1971-2019/, Dec. 9, 2019.
[2] K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill and H.-S. P. Wong, “Strained Si NMOSFETs for High Performance CMOS Technology,” Symposium on VLSI Technology, pp. 59-60, Jun. 2001. [3] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (IEDM), pp. 247-250, Dec. 2007. [4] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki and K. Mistry, “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” Symposium on VLSI Technology, pp. 131-132, Jun. 2012. [5] Seung Hyun Park, Yang Liu, Neerav Kharche, Mehdi Salmani Jelodar, Gerhard Klimeck, Mark S. Lundstrom and Mathieu Luisier, “Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm),” IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2107-2114, Aug. 2012. [6] 鍾奇諺, ”台積公司7奈米製程領先業界邁入量產,” available at: www.tsmc.com/csr/ch/update/innovationAndService/caseStudy/9/index.html, Jul. 20, 2018. [7] “International Roadmap for Devices and Systems, 2017 Edition, More Moore,” 2017. [8] Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang-Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, “Sub 50-nm FinFET: PMOS,” IEEE International Electron Devices Meeting (IEDM), pp. 67-70, Dec. 1999. [9] Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Charles Kuo, Erik Anderson, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000. [10] Yang-Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, Erik Anderson, Tsu-Jae King, Jeffrey Bokor and Chenming Hu, “Sub-20nm CMOS FinFET Technologies,” IEEE International Electron Devices Meeting (IEDM), pp. 421-424 Dec. 2001. [11] Bin Yu, Leland Chang, Shibly Ahmed, Haihong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery, Chau Ho, Qi Xiang, Tsu-Jae King, Jeffrey Bokor, Chenming Hu, Ming-Ren Lin and David Kyser, “FinFET Scaling to 10 nm Gate Length,” IEEE International Electron Devices Meeting (IEDM), pp. 251-254, Dec. 2002. [12] Tsung-Yang Liow, Kian-Ming Tan, Rinus T. P. Lee, Anyan Du, Chih-Hang Tung, Ganesh S. Samudra, Won-Jong Yoo, N. Balasubramanian and Yee-Chia Yeo, “Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement,” Symposium on VLSI Technology, pp. 56-57, Jun. 2006. [13] Kian-Ming Tan, Tsung-Yang Liow, Rinus T. P. Lee, Chih-Hang Tung, Ganesh S. Samudra, Won-Jong Yoo and Yee-Chia Yeo, “Drive-Current Enhancement in FinFETs Using Gate-Induced Stress,” IEEE Electron Device Letters, vol. 27, no. 9, pp. 769-771, Sep. 2006. [14] D. Guo, G. Karve, G. Tsutsui, K-Y Lim, R. Robison, T. Hook, R. Vega, D. Liu, S. Bedell, S. Mochizuki, F. Lie, K.Akarvardar, M. Wang, R. Bao, S. Burns, V. Chan, K. Cheng, J. Demarest, J. Fronheiser, P. Hashemi, J. Kelly, J. Li, N. Loubet, P. Montanini, B. Sahu, M. Sankarapandian, S. Sieg, J. Sporre, J. Strane, R.Southwick, N. Tripathi, R. Venigalla, J. Wang, K. Watanabe, C. W. Yeung, D. Gupta, B. Doris, N. Felix, A. Jacob, H. Jagannathan, S. Kanakasabapathy, R. Mo, V. Narayanan, D. Sadana, P. Oldiges, J. Stathis, T. Yamashita, V. Paruchuri, M. Colburn, A. Knorr, R. Divakaruni, H. Bu and M. Khare, “FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond,” Symposium on VLSI Technology, pp. 11-12 , Jun. 2016. [15] H. Mertens, R. Ritzenthaler, A. Hikavyy, J. Franco, J. W. Lee, D. P. Brunco, G. Eneman, L. Witters, J. Mitard, S. Kubicek, K. Devriendt, D. Tsvetanova, A. P. Milenin, C. Vrancken, J. Geypen, H. Bender, G. Groeseneken, W. Vandervorst, K. Barla, N. Collaert, N. Horiguchi and A.V-Y Thean, “Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins,” Symposium on VLSI Technology, pp. 48-49 , Jun. 2014. [16] J. Mitard, L. Witters, H. Arimura, Y. Sasaki, A.P. Milenin, R. Loo, A. Hikavyy, G. Eneman, P. Lagrain, H. Mertens, S. Sioncke, C. Vrancken, H. Bender, K. Barla, N. Horiguchi, A. Mocuta, N. Collaert and A.V-Y. Thean, “First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain,” IEEE International Electron Devices Meeting (IEDM), pp. 418-421, Dec. 2014. [17] J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L.-Å. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert and A.V-Y. Thean, “A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs,” Symposium on VLSI Technology, pp. 27-28 , Jun. 2016. [18] Yee-Chia Yeo, Xiao Gong, Mark J. H. van Dal, Georgios Vellianitis and Matthias Passlack, “Germanium-based Transistors for Future High Performance and Low Power Logic Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 28-31, Dec. 2015. [19] Dian Lei, Kwang Hong Lee, Shuyu Bao, Wei Wang, Saeid Masudy-Panah, Sachin Yadav, Annie Kumar, Yuan Dong, Yuye Kang, Shengqiang Xu, Ying Wu, Yi-Chiau Huang, Hua Chung, Schubert S. Chu, Satheesh Kuppurao, Chuan Seng Tan, Xiao Gong and Yee-Chia Yeo, “The First GeSn FinFET on a Novel GeSnOI Substrate Achieving Lowest S of 79 mV/decade and Record High Gm,int of 807 μS/μm for GeSn P-FETs,” Symposium on VLSI Technology, pp. 198-199 , Jun. 2017. [20] Dian Lei, Kaizhen Han, Kwang Hong Lee, Yi-Chiau Huang, Wei Wang, Sachin Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, Eugene Y.-J. Kong, Chuan Seng Tan and Xiao Gong, “GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V·s,” Symposium on VLSI Technology, pp. 197-198 , Jun. 2018. [21] Yuye Kang, Kaizhen Han, Eugene Y.-J. Kong, Dian Lei, Shengqiang Xu, Ying Wu, Yi-Chiau Huang and Xiao Gong, “The First GeSn Gate-All-Around Nanowire P-FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade,” International Symposium on VLSI Technology, Systems and Application (VLSI-TSA),pp. 112-113, Apr. 2019. [22] Yu-Shiang Huang, Fang-Liang Lu, Ya-Jui Tsou, Chung-En Tsai, Chung-Yi Lin, Chih-Hao Huang and C. W. Liu, “First vertically stacked GeSn nanowire pGAAFETs with Ion = 1850 μA/μm (Vov = Vds = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching,” IEEE International Electron Devices Meeting (IEDM), pp. 832-835, Dec. 2017. [23] Yu-Shiang Huang, Fang-Liang Lu , Ya-Jui Tsou, Hung-Yu Ye, Shih-Ya Lin, Wen-Hung Huang and C. W. Liu, “Vertically Stacked Strained 3-GeSn-Nanosheet pGAAFETs on Si Using GeSn/Ge CVD Epitaxial Growth and the Optimum Selective Channel Release Process,” IEEE Electron Device Letters, vol. 39, no. 9, pp. 1274-1277, Sep. 2018. [24] S. Gupta, B. Vincent, D. H. C. Lin, M. Gunji, A. Firrincieli, F. Gencarelli, B. Magyari-Köpe, B.Yang, B. Douhard, J. Delmotte, A. Franquet, M. Caymax, J. Dekoster, Y. Nishi and K.C. Saraswat, “GeSn Channel nMOSFETs: Material Potential and Technological Outlook,” Symposium on VLSI Technology, pp. 95-96 , Jun. 2012. [25] S. Gupta, B. Vincent, B. Yang, D. Lin, F. Gencarelli, J.-Y. J. Lin, R. Chen, O. Richard, H. Bender, B. Magyari-Köpe, M. Caymax, J. Dekoster, Y. Nishi and K. C. Saraswat, “Towards high mobility GeSn channel nMOSFETs: Improved surface passivation using novel ozone oxidation method,” IEEE International Electron Devices Meeting (IEDM), pp. 375-378, Dec. 2012. [26] Genquan Han, Shaojian Su, Lanxiang Wang, Wei Wang, Xiao Gong, Yue Yang, Ivana, Pengfei Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, Chunlai Xue, Buwen Cheng and Yee-Chia Yeo, “Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer,” Symposium on VLSI Technology, pp. 97-98 , Jun. 2012. [27] Pengfei Guo, Chunlei Zhan, Yue Yang, Xiao Gong, Bin Liu, Ran Cheng, Wei Wang, Jisheng Pan, Zheng Zhang, Eng Soon Tok, Genquan Han and Yee-Chia Yeo, “Germanium-Tin (GeSn) N-channel MOSFETs with low temperature silicon surface passivation Publisher: IEEE,” International Symposium on VLSI Technology, Systems and Application (VLSI-TSA),pp. 82-83, Apr. 2013. [28] Yung-Chin Fang, Kuen-Yi Chen, Ching-Heng Hsieh, Chang-Chia Su and Yung-Hsien Wu, “N-MOSFETs Formed on Solid Phase Epitaxially Grown GeSn Film with Passivation by Oxygen Plasma Featuring High Mobility,” ACS Applied Materials and Interfaces, pp. 26374-26380, Nov. 2015. [29] Tzu-Hung Liu, Po-Yuan Chiu, Yen Chuang, Chia-You Liu, Chang-Hong Shen, Guang-Li Luo and Jiun-Yun Li, “High-Mobility GeSn n-Channel MOSFETs by Low-Temperature Chemical Vapor Deposition and Microwave Annealing,” IEEE Electron Device Letters, vol. 39, no. 4, pp. 468-471, Apr. 2018. [30] Ravi Pillarisetty, “Academic and industry research progress in germanium nanodevices,” Nature, vol. 479, pp 324-328, Nov. 2011. [31] C. Schulte-Braucks, S. Glass, E. Hofmann, D. Stange, N. von den Driesch, J.M. Hartmann, Z. Ikonic, Q.T. Zhao, D. Buca and S. Mantl, “Process modules for GeSn nanoelectronics with high Sn-contents,” Solid-State Electronics, vol. 128, pp. 54-59, Feb. 2017. [32] Mingshan Liu, Genquan Han, Yan Liu, Chunfu Zhang, Hongjuan Wang, Xiangdong Li, Jincheng Zhang, Buwen Cheng and Yue Hao, “Undoped Ge0.92Sn0.08 quantum well PMOSFETs on (001), (011) and (111) substrates with in situ Si2H6 passivation: High hole mobility and dependence of performance on orientation,” Symposium on VLSI Technology, pp. 80-81 , Jun. 2014. [33] Kain Lu Low, Yue Yang, Genquan Han, Weijun Fan and Yee-Chia Yeo, “Electronic band structure and effective mass parameters of Ge1-xSnx alloys,” Journal of Applied Physics, vol. 112, no. 103715, pp. 1-9, Nov. 2012. [34] Jay Deep Sau and Marvin L. Cohen, “Possibility of increased mobility in Ge-Sn alloy system,” PHYSICAL REVIEW B, vol. 75, no. 045208, pp. 1-7, Jan. 2007. [35] Suyog Gupta, Blanka Magyari-K€ope, Yoshio Nishiand Krishna C. Saraswat, “Achieving direct band gap in germanium through integration of Sn alloying and external strain,” Journal of Applied Physics, vol. 113, no. 073707, pp. 1-7, Feb. 2013. [36] Genquan Han, Shaojian Su, Chunlei Zhan, Qian Zhou, Yue Yang, Lanxiang Wang, Pengfei Guo, Wang Wei, Choun Pei Wong, Ze Xiang Shen, Buwen Cheng and Yee-Chia Yeo, “High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules,” IEEE International Electron Devices Meeting (IEDM), pp. 402-404, Dec. 2011. [37] Suyog Gupta, Yi-Chiau Huang, Yihwan Kim, Errol Sanchez and Krishna C. Saraswat, “Hole Mobility Enhancement in Compressively Strained Ge0.93Sn0.07 pMOSFETs,” IEEE Electron Device Letters, vol. 34, no. 7, pp. 831-833, Jul. 2013. [38] Ruben R. Lieten , Tatsuro Maeda, Wipakorn Jevasuwan, Hiroyuki Hattori, Noriyuki Uchida, Shu Miura, Masatoshi Tanaka and Jean-Pierre Locquet, “Tensile-Strained GeSn Metal–Oxide–Semiconductor Field-Effect Transistor Devices on Si(111) Using Solid Phase Epitaxy,” Applied Physics Express, vol. 6, no. 101301, pp. 1-4, Sep. 2013. [39] Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park and Jean-Pierre Colinge, “Device design guidelines for nano-scale MuGFETs,” Solid-State Electronics, vol. 51, pp. 505-510, Mar. 2007. [40] Ran-Hong Yan, Abbas Ourmazd and Kwing F. Lee, “Scaling the Si MOSFET: From Bulk to SO1 to Bulk,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992. [41] Jean-Pierre Colinge, “FinFETs And Other Multi-Gate Transistor,” Springer, 2008. [42] H. Li, Y. X. Cui, K. Y. Wu, W. K. Tseng, H. H. Cheng and H. Chen, “Strain relaxation and Sn segregation in GeSn epilayers under thermal treatment,” Applied Physics Letters, vol. 102, no. 251907, pp. 1-4, Jun. 2013. [43] T.Y. Chan, J. Chen, P.K. KO and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” IEEE International Electron Devices Meeting (IEDM), pp. 718-721, Dec. 1987. [44] C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis and E. A. Fitzgerald, “Hole mobility enhancements and alloy scattering-limited mobility in tensile strained SiÕSiGe surface channel metal–oxide–semiconductor field-effect transistors,” Journal of Applied Physics, vol. 92, no. 7, pp. 3745-3751, Oct. 2002. [45] Chan-Hoon Park, Myung-Dong Ko, Ki-Hyun Kim, Chang-Woo Sohn, Chang Ki Baek, Yoon-Ha Jeong and Jeong-Soo Lee, “Comparative study of fabricated junctionless and inversion-mode nanowire FETs,” 69th Device Research Conference, pp. 179-180, Jun. 2011. [46] Shinji Migita, Yukinori Morita, Meishoku Masahara and Hiroyuki Ota, “Electrical performances of junctionless-FETs at the scaling limit (LCH= 3 nm),” IEEE International Electron Devices Meeting (IEDM), pp. 191-194, Dec. 2012. [47] Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain and Jean-Pierre Colinge, “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, no. 053511, pp. 1-2, Jan. 2009. [48] O. Kononchuk and B. Y. Nguyen, “Silicon-On-Insulator (SOI) Technology: Manufacture and Applications,” WOODHEAD PUBLISHING, 2014. [49] J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan and P. Razavi, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” Solid-State Electronics, vol. 65-66, pp. 33-37, Dec. 2011. [50] Renan Doria Trevisoli , Rodrigo Trevisoli Doria, Michelly de Souza and Marcelo Antonio Pavanello, “Threshold voltage in junctionless nanowire transistors,” Semiconductor Science and Technology, vol.26, no. 105009, pp. 1-8, Sep. 2011. [51] Renan Doria Trevisoli, Rodrigo Trevisoli Doria, Michelly de Souza, Marcelo Antonio Pavanello, “A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors,” Solid-State Electronics, vol. 90, pp. 12-17, Dec. 2013. [52] Jae Hur, Byung-Hyun Lee, Min-Ho Kang, Dae-Chul Ahn, Tewook Bang, Seung-Bae Jeon and Yang-Kyu Choi, “Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode,” IEEE Electron Device Letters, vol. 37, no. 5, pp. 541-544, May. 2016. [53] Chi-Woo Lee, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi and Jean-Pierre Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electronics, vol. 54, pp. 97-103, Feb. 2010. [54] Wei Wang, Dian Lei, Yuan Dong, Xiao Gong, Eng Soon Tok and Yee-Chia Yeo, “Digital Etch Technique for Forming Ultra-Scaled Germanium-Tin (Ge1−xSnx) Fin Structure,” Scientific Reports, no. 1835, pp. 1-9, May. 2017. [55] G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” Journal of Applied Physics, vol. 89, no. 10, pp. 5243-5275, May. 2001. [56] Jiuren Zhou, Genquan Han, Yue Peng, Yan Liu, Jincheng Zhang, Qing-Qing Sun, David Wei Zhang and Yue Hao, “Ferroelectric Negative Capacitance GeSn PFETs With Sub-20 mV/decade Subthreshold Swing,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1157-1160, Aug. 2017. [57] Lanxiang Wang, Shaojian Su, Wei Wang, Xiao Gong, Yue Yang, Pengfei Guo, Guangze Zhang, Chunlai Xue, Buwen Cheng, Genquan Han and Yee-Chia Yeo, “(NH4)2S Passivation for High Mobility Germanium-Tin (GeSn) p-MOSFETs,” International Silicon-Germanium Technology and Device Meeting (ISTDM), pp. 1-2, Jun. 2012. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74663 | - |
| dc.description.abstract | 自從1960年代摩爾定律被提出後，電晶體等邏輯元件便跟隨摩爾定律持續微縮至今。為了提升元件效能以延續摩爾定律，以具更高載子遷移率的新材料如鍺或鍺錫，來作為電晶體的通道材料，是一個可行的選項。鍺錫合金的電洞遷移率，可藉由施加壓縮應變來提升；而電子遷移率則可藉由將電子聚集在等效質量較小的Γ能帶來提升。目前為止已有高效能的p-型鍺錫電晶體被發表，然而關於n-型鍺錫電晶體的相關研究至今卻十分稀少，且效能相較p-型鍺錫電晶體偏低。
本論文製作出n-型鍺錫平面電晶體以及n-型鍺錫鰭式電晶體。與平面電晶體相比，鰭式電晶體在導通電流以及次臨界擺幅表現上有顯著的提升。鰭式電晶體的最佳表現為100 μA/μm導通電流(在VOV = 1 V)與170 mV/dec次臨界擺幅，且隨著通道長度與通道寬度微縮，電晶體表現會因更佳的閘極對通道控制能力，而進一步提升。除了反轉式鍺錫鰭式電晶體，論文中也製作出無接面式鍺錫鰭式電晶體。由於鍺錫合金相較於矽、鍺具有較差的熱預算及熱穩定性，降低熱預算是鍺錫電晶體製程的一大重點。無接面鍺錫鰭式電晶體由於可避免載子活化的熱製程步驟，因此整體製程的熱預算得以降低，使得表現優於反轉式鍺錫鰭式電晶體。n-型濃摻雜的鍺錫合金，可藉由化學氣相沉積方式，在鍺錫合金磊晶過程中以內摻雜技術來成長。完成之無接面鍺錫鰭式電晶體，在導通電流、次臨界擺幅與電流開關比表現上，均優於反轉式鍺錫鰭式電晶體，最佳表現為200 μA/μm導通電流(在VOV = 1 V)、90 mV/dec次臨界擺幅與106電流開關比(在VOV = 1 V)，是目前發表之n-型鍺錫電晶體的紀錄。 | zh_TW |
| dc.description.abstract | Logic devices such as MOSFETs have been scaled down since 1960’s by following Moore’s law. To continue Moore’s law for better device performance, new channel materials with high mobility such as germanium or germanium-tin (GeSn) are required. Hole mobility can be boosted in GeSn by compressive strains and electron population in the Γ-band of GeSn can enhance electron mobility due to its smaller effective mass. While high-performance GeSn p-MOSFETs were demonstrated, GeSn n-MOSFETs ween underdeveloped.
In this thesis, n-type GeSn planar MOSFETs and FinFETs were fabricated. Significant improvement of drive current and subthreshold swing (SS) for FinFETs were demonstrated compared to planar FETs. The highest drive current is 100 μA/μm with an overdrive voltage of 1 V and the best SS is 170 mV/decade. The drive current and subthreshold swing can be improved as the devices are scaled down due to the great gate control of the FinFET structure. In addition to the inversion-mode devices, junctionless (JL) GeSn FinFETs were also fabricated. For JL FinFETs, the dopant activation process can be avoided to save thermal budget, which is crucial for GeSn due to its poor thermal stability. By in-situ doping technique, n-GeSn films were epitaxially grown by chemical vapor deposition. The JL devices show better drive current, subthreshold swing, and Ion/Ioff ratios compared to the inversion-mode devices. The highest drive current is 200 μA/μm with an overdrive voltage of 1 V, the best SS is 90 mV/dec subthreshold swing, and the highest Ion/Ioff ratio is 106 with an overdrive voltage of 1 V, which are the best reported performance among the demonstrated GeSn n-MOSFETs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T09:05:45Z (GMT). No. of bitstreams: 1 ntu-109-R06943066-1.pdf: 4015412 bytes, checksum: ee91b4d7a384437ff3ecbd53b0bc0543 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii Abstract iv 目錄 v-vi 圖目錄 vii-ix 表目錄 x 第一章 引言 1 1.1 鰭式金氧半場效電晶體 3 1.2 鍺錫通道材料 5 1.3 論文架構 8 第二章 n-型鍺錫平面與鰭式電晶體 9 2.1 鰭式電晶體簡介 9 2.2 鍺錫薄膜磊晶與分析 14 2.3 鍺錫平面電晶體製作與分析 16 2.4 反轉式鍺錫鰭式電晶體製作與分析 21 2.4 小結 27 第三章 無接面n-型鍺錫鰭式電晶體 28 3.1 無接面電晶體簡介 28 3.2 鍺錫薄膜磊晶與分析 33 3.3 無接面鍺錫鰭式電晶體製作與分析 35 3.4 小結 43 第四章 結論與未來工作 45 4.1 結論 45 4.2 未來工作與展望 46 參考文獻 47 | |
| dc.language.iso | zh-TW | |
| dc.subject | 載子遷移率 | zh_TW |
| dc.subject | 鰭式電晶體 | zh_TW |
| dc.subject | 鍺錫合金 | zh_TW |
| dc.subject | 無接面 | zh_TW |
| dc.subject | 導通電流 | zh_TW |
| dc.subject | 次臨界擺幅 | zh_TW |
| dc.subject | subthreshold swing | en |
| dc.subject | germanium-tin (GeSn) | en |
| dc.subject | drive current | en |
| dc.subject | FinFETs | en |
| dc.subject | mobility | en |
| dc.subject | junctionless (JL) | en |
| dc.title | n-型鍺錫反轉式及無接面式鰭式電晶體製作與分析 | zh_TW |
| dc.title | Fabrication and characterization of n-type GeSn
inversion mode and junctionless mode FinFETs | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 廖洺漢,陳敏璋,李敏鴻 | |
| dc.subject.keyword | 鍺錫合金,鰭式電晶體,無接面,次臨界擺幅,載子遷移率,導通電流, | zh_TW |
| dc.subject.keyword | germanium-tin (GeSn),FinFETs,junctionless (JL),subthreshold swing,mobility,drive current, | en |
| dc.relation.page | 57 | |
| dc.identifier.doi | 10.6342/NTU202000053 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-01-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-109-1.pdf 未授權公開取用 | 3.92 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。