微波多層被動電路之佈局對電路檢查的後段與立體圖形多使用者介面

Abstract

本篇論文主要針對微波被動多層電路佈局圖驗證工具進行優化，我們設計該工具時主要分成兩個部分，分別是從佈局圖中萃取元件輸出成網路表格式的前段部分，以及比對原先電路設計圖網路表和由前段萃取的佈局圖網路表之間差異的後段部分，本篇論文將著重在討論對於後段部分的修改。 原先後段部分的演算法是根據每個節點相鄰的電感值和電容值給予該節點一個權重，再將原先設計圖的節點和佈局圖的節點進行配對，藉此找出兩邊的元件使否存在差異，但有機會出現很多種可能的配對組合，需要再花費時間篩選正確的配對組合。本篇論文加入了新的比對方式，由電路外部已知的連接埠逐步向電路內部進行比對，避免出現因元件值相同而比對錯誤的情況，且能藉由電路元件之間的連接關係降低計算比對的時間。 另外，我們也在先前所開發的立體圖形化多使用者介面中融合了從佈局圖中萃取元件和進行電路圖和佈局圖比對的部分，並製作了兩款Android平台的app提供使用者在行動裝置上使用該介面，分別是與在個人電腦上的介面功能相同的行動版，以及需要額外搭配手機放置盒使用、可以達到立體顯影的VR版，讓使用者在使用這套軟體時可以獲得更完整的體驗。

An optimized algorithm of layout versus schematic checker is presented in this thesis. The checker is divided into two parts. First, the component extraction from layout would be exported to net-list. Second, we would compare the discrepancy of the net-lists between schematic and layout of microwave multilayer passive circuits. The previous algorithm uses weight vectors that are related to inductance and capacitance of devices connected to a node. By comparing the weight of vectors, we can find out the difference between layout and schematic. However, we need to spend some time to pick and match if many possible mappings are found. In this thesis, we will start the mapping from known ports that connect circuit to external devices. Through searching for the relative position between the components from the ports, the comparison errors associated with the same components values can be avoided and the computational time can be minimized. In addition, we integrated the display of schematic and layout in microwave multilayer passive circuits and components from layout in 3-D graphical interface. We also develop a general version app and a VR version app of 3-D graphical interface. Therefore, microwave circuit designers can use this tool to debug circuits more efficiently.