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DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 闕志達(Tzi-Dar Chiueh) | |
dc.contributor.author | Po-En Su | en |
dc.contributor.author | 蘇伯恩 | zh_TW |
dc.date.accessioned | 2021-06-17T08:24:45Z | - |
dc.date.available | 2021-02-22 | |
dc.date.copyright | 2021-02-22 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2021-01-25 | |
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SPECIFICATIONS USRP-2943 Software Defined Radio Reconfigurable Device. Accessed: Dec. 16, 2020. [Online]. Available: https://www.ni.com/pdf/manuals/374193d.pdf [24] Ettus. USRP Hardware Driver and USRP Manual. Accessed: Dec. 16, 2020. [Online]. Available: https: https://files.ettus.com/manual/ [25] Github. uhd/host/examples/rx_samples_to_file.cpp. Accessed: Dec. 16, 2020. [Online]. Available: https://github.com/EttusResearch/uhd/blob/master/host/examples/rx_samples_to_file.cpp [26] NI. USRP-2943 120 MHz Block Diagram. Accessed: Dec. 17, 2020. [Online]. Available: https://www.ni.com/documentation/en/usrp-software-defined-radio-reconfigurable-device/latest/usrp-2943-120mhz/block-diagram/ [27] Xilinx. Alveo U250 Data Center Accelerator Card. Accessed: Dec. 16, 2020. [Online] Available: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html [28] Xilinx. Alveo Product Brief Guide. Accessed: Dec. 16, 2020. [Online]. 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Xilinx CORDIC v6.0 LogiCORE IP Product Guide. Accessed: Dec. 18, 2020. [Online]. Available: https://www.xilinx.com/support/documentation/ip_documentation/cordic/v6_0/pg105-cordic.pdf [34] Xilinx. Xilinx Divider Generator v5.1 LogiCORE IP Product Guide. Accessed: Dec. 18, 2020. [Online]. Available: https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf [35] 3GPP. 5G NR Multiplexing and channel coding, 3GPP TS 38.212 version 15.9.0 Release 15, Jul. 2020. Accessed: Dec. 18, 2020. Accessed: Dec. 16, 2020. [Online]. Available: https://portal.3gpp.org/desktopmodules/Specifications/SpecificationDetails.aspx?specificationId=3214 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74216 | - |
dc.description.abstract | 時代一直在進步,無論是一般大眾或者是公司企業,對於無線連網的需求變得越來越高,應用範疇更是包羅萬象,舉凡居家、交通、娛樂、醫療、工廠生產,很多以前科幻電影的畫面,甚至是人們從沒想過的場景都被逐步地實現,而能夠實現的原因很大一部份要歸功於新世代通訊系統能夠提供更高的資料傳輸速率,還有容許更多裝置在同一時間內連網。當同時間連網的裝置變多的時候,傳統的無線通訊系統是透過時間或是頻率的分隔來達到多重接取的效果,如時間分工多重接取 (TDMA)、頻率分工多重接取 (FDMA)等等,但由於頻譜資源有限,若連網裝置的數量持續增加勢必會遇到資源不夠的情況,這時利用空間分工多重接取 (Spatial Division Multiple Access, SDMA)將不同使用者所傳送的資料分開來,就能再提升整體系統的效能。 本論文基於現有的波束成形理論,選擇Xilinx Alveo U250 FPGA加速平台,並參考5G NR的規範來實作多使用者多輸入單輸出波束成形 (Multi-User MISO Beamforming)硬體內接收機 (Inner Receiver)。此內接收機負責將使用者的時域IQ資料經過載波頻率偏移補償以及傅立葉轉換轉成頻域後,進行通道估測,並且將訊號等化後輸出星座點給軟體進一步做外接收機 (Outer Receiver)解碼。 本內接收機系統包含了軟體端和硬體端,分別負責輸入輸出資料的控制和資料的運算,而這樣的分配正是基於軟體的高度彈性和硬體的強大運算能力。要正確地解出資料就需要軟體和硬體之間的合作,而這兩者順利溝通的關鍵就是我們透過狀態暫存器 (Status Register)來讓雙方知道目前系統運作的狀況,實際上做法就是軟體端會去存取FPGA上特定記憶體位置的資料,而硬體內部的RTL程式也會存取同樣記憶體位置的資料,所以我們可以事先定義不同的數字代表什麼狀態,讓軟體端和硬體端根據當下的狀態去存取這個狀態暫存器來達到溝通效果。 使用硬體來實現內接收機就是為了加快接收端解碼的速度,進一步實現即時(Real-time)解碼的效果。為了驗證本論文所設計的系統之正確性及可行性,我們在空氣通道 (Over-The-Air)的環境裡傳送影片檔給本接收端系統,並將內接收機解碼完的星座點送給外接收機進行錯誤更正碼解碼。最後解碼後的結果可以達到Block Error Rate = 0,並順利在接收端將影片重新播放出來。而解碼時間大約等同於影片傳送的時間。 | zh_TW |
dc.description.abstract | Over the past few years, people have been asking for more from wireless Internet. There are growing demands from education, traffic, entertainment, medical purpose, factory production, etc. Many of the applications that only existed in sci-fi movies are now realized in our world. One of the reasons for these real-world sci-fi applications is that the new generation communication systems provide higher data transmission rates and allow more devices to connect to the Internet at the same time. Traditionally, wireless communication systems separate user data in the time domain or the frequency domain to achieve multiple access, such as Time Division Multiple Access (TDMA) or Frequency Division Multiple Access (FDMA). However, the spectrum is precious and limited, and it will inevitably become insufficient when more and more devices are trying to get connected. Therefore, separate user data in the space domain, namely Spatial Division Multiple Access (SDMA), can help ease the insufficiency and improve the overall system performance. We’ve built a Multi-User MISO (MU-MISO) Beamforming Inner Receiver system based on the existing beamforming theories and 5G NR specifications. This inner Rx system is built on the Xilinx Alveo U250 FPGA platform. It can compensate the CFO of the input time-domain IQ data, take FFT to convert it to frequency-domain data, and then perform channel estimation and equalization. The equalized constellations will be sent to a software-based outer receiver for further decoding. This inner receiver system contains both software and hardware, which are in charge of input/output data control and baseband processing, respectively. This is because the software has high flexibility, while the hardware owns outstanding performance. In order to decode the data correctly, the software must cooperate with the hardware, and the key to make this happen is to use a “status register” to let them communicate with each other. The software program will access the data stored in specific SRAM on the FPGA, and the hardware module will access the same data as well. By using pre-defined values that stand for different status, both software program and hardware module can write a status register to notify each other of their current status or read the status register to know each other’s status, and when one side executes, the other side waits. Adopting hardware to implement inner receiver aims for speeding up the decoding progress and achieving the effect of decoding data in real-time. In order to verify the correctness and feasibility of the system in this thesis, we transmitted a video through OTA channel, and decoded the OTA signals with this inner Rx system and sent the output constellations to software outer Rx for LDPC decoding and so on so forth. The decoded results showed that the BLER was 0, and the video could be played at the receiver side without any error. The elapsed time for decoding data about the same as the OTA transmission time. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T08:24:45Z (GMT). No. of bitstreams: 1 U0001-2501202112120900.pdf: 9564112 bytes, checksum: 1c3d0e2cbb2ffccaeddd4f4bf3ca8667 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 致謝 i 摘要 iii Abstract v 目錄 vii 圖目錄 xi 表目錄 xvi 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 2 1.3 論文架構 3 第二章 5G NR實體層介紹 5 2.1 3GPP 第五代行動通訊新無線電 (5G NR)簡介 5 2.1.1 訊框架構 (Radio Frame Structure) 5 2.1.2 波型參數 (Numerology) 8 2.1.3 解調參考訊號 (Demodulation Reference Signal) 12 2.1.4 同步訊號 (Synchronization Signal) 17 2.1.4.1 主要同步訊號 (Primary Synchronization Signal, PSS) 19 2.1.4.2 次要同步訊號 (Secondary Synchronization Signal, SSS) 20 2.2 波束成形 (Beamforming) 20 2.2.1 天線陣列 (Antenna Array) 21 2.2.2 原理介紹 23 2.2.3 波束方向圖模擬 26 2.2.4 波束方向圖量測 28 第三章 內接收機系統架構 31 3.1 接收機架構 31 3.2 內接收機各模組介紹 31 3.2.1 同步訊號塊偵測 (SSB Detection) 32 3.2.1.1 同步訊號區塊(Synchronization Signal Block, SSB) 32 3.2.1.2 交叉相關性 (Cross Correlation) 33 3.2.2 符元邊界粗估 (CSBD) 34 3.2.3 分數載波偏移補償 (FCFO Compensation) 35 3.2.4 整數載波偏移補償 (ICFO Compensation) 37 3.2.5 循環前綴移除 (CP Removal) 40 3.2.6 快速傅立葉轉換 (Fast Fourier Transform, FFT) 41 3.2.7 解調參考訊號擷取 (DMRS Extraction) 43 3.2.7.1 解調參考訊號 (DeModulation-Reference Signal, DMRS) 43 3.2.7.2 解調參考訊號擺放位置 (DMRS Pattern) 45 3.2.8 通道估測 (Channel Estimation) 46 3.2.9 訊號等化 (Equalization) 49 第四章 接收端現場可程式化邏輯閘陣列(FPGA)之內接收機設計與實現 51 4.1 系統架構 51 4.2 軟體端 52 4.2.1 軟體定義無線電介紹 52 4.2.2 通用軟體無線電周邊設備 (USRP) 53 4.2.3 USRP驅動程式 (USRP Hardware Driver, UHD) 56 4.2.4 FPGA控制程式 (FPGA Control C Program) 57 4.2.4.1 讀寫輸入與輸出資料 57 4.2.4.2 重傳輸入資料 59 4.2.4.3 狀態暫存器 (Status Register) 59 4.3 硬體端 60 4.3.1 Xilinx Alveo U250簡介 61 4.3.2 內接收機模組介紹 62 4.3.2.1 接收機介面模組 (Rx I/O Module) 64 4.3.2.2 交叉相關性計算 (Cross Correlation) 66 4.3.2.3 同步訊號塊波峰偵測 (SSB Peak Detection) 69 4.3.2.4 相關性計算 (Correlation) 71 4.3.2.5 分數載波頻率飄移偵測 (Fractional CFO Acquisition) 72 4.3.2.6 分數載波頻率飄移補償 (Fractional CFO Compensation) 72 4.3.2.7 整數載波頻率飄移偵測 (Integral CFO Detection) 72 4.3.2.8 整數載波頻率飄移補償 (Integral CFO Compensation) 74 4.3.2.9 快速傅立葉轉換控制模組 (FFT Window Control) 74 4.3.2.10 快速傅立葉轉換 (FFT) 75 4.3.2.11 通道估測與等化 (Channel Estimation and Equalization) 76 4.4 接收端系統總結 90 第五章 接收端現場可程式化邏輯閘陣列(FPGA)之成果展示 92 5.1 OTA展示成果 92 5.1.1 展示規格 93 5.1.2 展示環境及流程 94 5.1.3 即時解碼結果 95 5.2 內接收機系統實驗 101 5.2.1 訊號開頭偵測實驗 101 5.2.2 錯誤率實驗 101 5.2.3 調變訊號實驗 105 第六章 結論與展望 108 6.1 論文總結 108 6.2 未來展望 110 參考文獻 112 | |
dc.language.iso | zh-TW | |
dc.title | 第五代行動通訊新無線電多使用者多輸入單輸出波束成形系統即時內接收機之設計與實現 | zh_TW |
dc.title | Design and Real-time Implementation of 5G NR Inner Receiver for MU-MISO Beamforming System | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡佩芸(Pei-Yun Tsai),馬席彬(Hsi-Pin Ma),伍紹勳(Sau-Hsuan Wu) | |
dc.subject.keyword | 即時 (Real-time),空氣通道 (OTA),現場可編程邏輯閘陣列 (FPGA),第五代行動通訊新無線電 (5G NR),內接收機 (Inner Receiver),多輸入單輸出 (MISO), | zh_TW |
dc.subject.keyword | Real-time,Over-The-Air (OTA),FPGA,5G NR,inner receiver,MISO, | en |
dc.relation.page | 115 | |
dc.identifier.doi | 10.6342/NTU202100152 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2021-01-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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