FPGA資源感知下非同步電路之合成與安全AES設計之案例研究

Abstract

非同步電路相較於同步電路而言有很多獨特的優點。例如：對於旁路攻擊 (side-channel attack) 有較高的安全性；能彈性地面對運作時間差異與突發的環境波動；對電磁干擾有較高的容忍度；組合不同的模塊相對容易；還有許多其他的優點。 在眾多非同步電路的延遲模型中，雙軌編碼 (dual-rail encoding)的類延遲非敏感 (quasi-delay insensitive, QDI) 電路是一種可行的模型，因為其少許的時間假設，以及足夠的時間強韌度。此外，雙軌預先充電邏輯 (dual-rail precharge logic) 已被視為是一種可行的對策去降低功率消耗時洩漏的資訊。 在另一方面，電場可程式化邏輯閘陣列 (FPGA) 中因其可重構性 (reconfigurability) 被視為是系統單晶片 (SoC) 設計中的重要單元。相對於特定應用積體電路(ASIC)，FPGA的可重構性也可以提供一個方便的流程去調整設計去對抗透過實際測量的旁路攻擊。但要將QDI的電路放在同步電路架構的FPGA板上是具有挑戰性的，因有資源上的限制。 在此篇論文中，我們對於非同步電路的基本元件在同步電路FPGA提出有效的實作方式，並提出一自動化的設計流程，使得我們得以快速地合成更複雜的非同步電路設計。此外，我們提出了同步與非同步之間的介面轉換，方便非同步與主流的同步電路溝通。最後，為了確認我們合成架構的可行性，我們實作出一個以非同步的進階加密標準 (AES) ，並執行差分能量分析 (DPA) 的實驗，去證明非同步AES相對於同步電路架構的安全性。

Asynchronous circuits have distinct advantages over their synchronous counterparts, e.g., in their security against side-channel attacks, resilience against process variation, robustness against environmental fluctuation, low electromagnetic interference, and ease of design composition, among other benefits. Among various asynchronous delay models, quasi-delay insensitive (QDI) circuits with dual-rail encoding are promising due to its relaxed timing assumption and timing robustness. Furthermore, dual-rail precharge logic (DRPL) has been considered to be a practical countermeasure method to mitigate information leakage in power consumption by dual-rail encoding. On the other hand, FPGA implementation becomes an essential building block in system-on-a-chip (SoC) design due to its reconfigurability. Compared to ASIC implementation, the reconfigurability of FPGAs also provides a convenient procedure for design adjustment against side-channel attacks through physical measurements. However, mapping QDI circuits on FPGA is challenging due to limited resources. In this thesis, we propose the effective implementation of asynchronous basic units on synchronous-based FPGA and show the design automation flow to synthesize more complex asynchronous design quickly. Besides, we propose the interface between synchronous and asynchronous domain for data transmission. Finally, to confirm the feasibility of our synthesis framework, we realize an Advanced Encryption Standard (AES) design and perform differential power analysis (DPA) to justify the security of asynchronous AES compared to its synchronous counterparts.