基於模擬的功能性限制抽取應用於軟體自我測試

Abstract

由於傳統基於掃描的超大型積體電路測試的不足，軟體自我測試在功能模式下執行測試程式來偵測錯誤，其具有非侵入性、功能性以及可全速測試，被認為是一個有前途的測試方法。 功能性限制抽取在使用自動測試圖樣產生輔助的產生測試程式方法中佔了重要的地位，至今仍然普遍採取人工的功能性限制抽取，然而，這會需要大量的專業知識和對處理器架構的熟悉度，隨著處理器複雜度的增加，人工的功能性限制抽取顯得越來越不足。本篇論文發展了一個自動化的功能性限制抽取方法。 本篇論文提出的自動化功能性限制抽取方法使用了基於模擬的資料挖掘技術，目標是降低尋找限制的人工需求，結果顯示此方法也會大量的降低測試程式的大小。最終產生的測試程式也會被用來偵測轉態延遲錯誤(transition delay fault)，結果顯示與人工的功能性限制抽取相比，只有些微的錯誤覆蓋率降低。

Due to the insufficiency of conventional scan-based VLSI testing, Software-based self-testing (SBST) has been recognized as a promising alternative which executes test programs in functional mode to detect faults. Thus SBST is non-intrusive, functional and at-speed, and be considered as a promising approach. Constraint extraction plays an important role in ATPG-aided test program generation approach for SBST. Nowadays, manual constraint extraction is still used generally. However, it needs a lot of domain knowledge and the familiarity with the design architecture. The increasing complexity of the processor would lead manual constraint extraction to be more difficult and insufficient. This thesis has developed an automatic approach for extracting constraints. The proposed SBST automatic functional constraint extraction methodology applies a simulation-based data mining technique. The objective is to reduce human effort on finding constraints. The result shows that it can also dramatically decrease the test program size. The test program is also used to detect transition delay fault, while there is just a tiny loss of the fault coverage compared with manual constraint extraction.