請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73440完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王暉(Huei Wang) | |
| dc.contributor.author | Yang Chang | en |
| dc.contributor.author | 張洋 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:35:01Z | - |
| dc.date.available | 2024-05-10 | |
| dc.date.copyright | 2019-05-10 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-05-04 | |
| dc.identifier.citation | [1] D. Zhao and P. Reynaert, CMOS 60-GHz and E-band Power Amplifiers and Transmitters. Switzerland: Springer International Publishing, 2015.
[2] Noël Deferm and P. Reynaert, CMOS Front Ends for Millimeter Wave Wireless Communication System. Switzerland: Springer International Publishing, 2015. [3] John G. Proakis and Masoud Salehi, Communication Systems Engineering, 2nd, Prentice Hall, 2001. [4] J.-L. Lin, “Design of high efficiency millimeter wave power amplifiers and simulation and measurement of digitally modulated signal,” Master dissertation, National Taiwan University, January, 2018. [5] P.-H. Chen, H.-K. Chiou and Y.-C. Wang, “A K-band 24.1% PAE wideband unilateralized CMOS power amplifier using differential transmission-line transformers in 0.18-μm CMOS,” in IEEE Microwave and Wireless Components Letters, vol. 26, no. 11, pp. 924-926, Nov. 2016. [6] S. R. Helmi, J.-H. Chen and S. Mohammadi, “High-efficiency microwave and mm-wave stacked cell CMOS SOI power amplifiers,” in IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 7, pp. 2025-2038, July 2016. [7] J.-L. Lin, Y.-H. Lin, Y.-H. Hsiao and H. Wang, “A K-band transformer based power amplifier with 24.4-dBm output power and 28% PAE in 90-nm CMOS technology,” in IEEE MTT-S International Microwave Symposium (IMS), Honolulu, HI, Jun 2017. [8] S. N. Ali, et al., “A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable gate-drain neutralization for 28-GHz 5G radios,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 5, pp. 2231-2245, May 2018. [9] W.-C. Huang, et al., “A K-band power amplifier with 26-dBm output power and 34% PAE with novel inductance-based neutralization in 90-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, Jun. 2018. [10] J. A. Jayamon, et al., “Multigate-cell stacked FET design for millimeter-wave CMOS power amplifiers,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 9, pp. 2027-2039, Sept. 2016. [11] Y.-C. Lee, et al., “An adaptively biased stacked power amplifier without output matching network in 90-nm CMOS,” in IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, Jun. 2017. [12] S.-H. Chang, et al., “A Ka-band dual-mode power amplifier in 65-nm CMOS technology,” in IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 708-710, Aug. 2018. [13] Y.-C. Chen, et al., “A Ka-band transformer-based Doherty power amplifier for multi-Gb/s application in 90-nm CMOS,” in IEEE Microwave and Wireless Components Letters, Nov. 2018. [14] H.-T. Dabag, et al., “Analysis and design of stacked-FET millimeter-wave power amplifiers,” in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 4, pp. 1543-1556, April. 2013. [15] Y.-H. Hsiao, Z.-M. Tsai, H.-C. Liao, J.-C. Kao and H. Wang, “Millimeter-wave CMOS power amplifiers with high output power and wideband performances,” in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4520-4533, Dec. 2013. [16] D. Zhao and P. Reynaert, “A 60-GHz dual-mode Class AB power amplifier in 40-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2323-2337, Oct. 2013. [17] J.-F. Yeh, Y.-F. Hsiao, J.-H. Tsai and T.-W. Huang, “MMW ultra-compact n-way transformer PAs using bowtie-radial architecture in 65-nm CMOS,” in IEEE Microwave and Wireless Components Letters, vol. 25, no. 7, pp. 460-462, July 2015. [18] A. Larie, E. Kerhervé, B. Martineau, L. Vogt and D. Belot, “A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2015. [19] M. Bassi, J. Zhao, A. Bevilacqua, A. Ghilioni, A. Mazzanti and F. Svelto, “A 40–67 GHz power amplifier with 13 dBm Psat and 16% PAE in 28 nm CMOS LP,” in IEEE Journal of Solid-State Circuits, vol. 50, no. 7, pp. 1618-1628, July 2015. [20] C.-F. Chou, Y.-H. Hsiao, Y.-C. Wu, Y.-H. Lin, C.-W. Wu and H. Wang, “Design of a V-band 20-dBm wideband power amplifier using transformer-based radial power combining in 90-nm CMOS,” in IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 12, pp. 4545-4560, Dec. 2016. [21] J. Xia, A. Chung and S. Boumaiza, “A wideband millimeter-wave differential stacked-FET power amplifier with 17.3 dBm output power and 25% PAE in 45nm SOI CMOS,” in IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, Jun. 2017. [22] S.-M. Weng, Y.-C. Lee, T.-H. Chen and J. Y.-C. Liu, “A 60-GHz adaptively biased power amplifier with predistortion linearizer in 90-nm CMOS,” in IEEE MTT-S International Microwave Symposium (IMS), Philadelphia, PA, Jun. 2018. [23] K. Ning and J. F. Buckwalter, “An 18-dBm, 57 to 85-GHz, 4-stack FET power amplifier in 45-nm SOI CMOS,” in IEEE MTT-S International Microwave Symposium (IMS), Philadelphia, PA, Jun. 2018. [24] J. Xia, X.-H. Fang and S. Boumaiza, “60-GHz power amplifier in 45-nm SOI-CMOS using stacked transformer-based parallel power combiner,” in IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 711-713, Aug. 2018. [25] C.-W. Wu, Y.-H. Lin, Y.-H. Hsiao, C.-F. Chou, Y.-C. Wu and H. Wang, “Design of a 60-GHz high-output power stacked-FET power amplifier using transformer-based voltage-type power combining in 65-nm CMOS,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 10, pp. 4595-4607, Oct. 2018. [26] L. Rakotondrainibe, Y. Kokar, G. Zaharia and G. El Zein, “60 GHz high data rate wireless communication system,” in IEEE 69th Vehicular Technology Conference, Barcelona, Apr. 2009. [27] R. C. Daniels and R. W. Heath, “60 GHz wireless communications: emerging requirements and design recommendations,” in IEEE Vehicular Technology Magazine, vol. 2, no. 3, pp. 41-50, Sept. 2007. [28] T. S. Rappaport, et al., “Millimeter wave mobile communications for 5G cellular: It will work!,” in IEEE Access, vol.1, pp.335-349, May. 2013. [29] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi and P. M. Asbeck, “A watt-level stacked-FET linear power amplifier in Silicon-on-insulator CMOS,” in IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 1, pp. 57–64, Jan. 2010. [30] H.-T. Dabag, B. Hanafi, F. Golcuk, A. Agah, J. F. Buckwalter and P. M. Asbeck, “Analysis and design of stacked-FET millimeter-wave power amplifiers,” in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 4, pp. 1543-1556, April. 2013. [31] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001. [32] K. L. Fong and R. G. Meyer, “High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages,” in IEEE Journal of Solid-State Circuits, vol. 33, no. 4, pp. 548-555, April 1998. [33] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Boston, MA: Artech House, 2000. [34] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin and K. Entesari, “A highly efficient and linear power amplifier for 28-GHz 5G phased array radios in 28-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3020-3036, Dec. 2016. [35] Y. Zhang and P. Reynaert, “A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, Jun. 2017. [36] X. Guan and A. Hajimiri, “A 24-GHz CMOS front-end,” in IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 368-373, Feb. 2004. [37] A. Basaligheh, et al., “A highly efficient and linear broadband common-drain CMOS power amplifier with transformer-based input-matching network,” in IEEE Microwave and Wireless Components Letters, vol. 25, no. 12, pp. 814-816, Dec. 2015. [38] A. F. Aref, et al., “Class-O: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2015, pp. 1-3. [39] M.-D. Wei and R. Negra, “Highly linear fully integrated class-O power amplifier in standard 65 nm CMOS technology,” in IEEE 11th European Microwave Integrated Circuits Conference (EuMIC), London, Oct. 2016, pp. 413-416. [40] M. A. Khan and R. Negra, “Common-drain CMOS power amplifier: An alternative power amplifier,” in IEEE 12th European Microwave Integrated Circuits Conference (EuMIC), Nuremberg, Oct. 2017, pp. 285-288. [41] V. Paidi, et al., “High linearity and high efficiency of class-B power amplifiers in GaN HEMT technology,” in IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 2, pp. 643-652, Feb. 2003. [42] M. A. Khan, D. Kalim and R. Negra, “Analysis and design of an unconditionally stable common-drain class-B RF power amplifier in 90 nm CMOS technology,” in 2011 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, Vienna, Apr. 2011, pp. 1-4. [43] J. M. Rollett, “Stability and power-gain invariants of linear twoports,” in IEEE IRE Transactions on Circuit Theory, vol. 9, no. 1, pp. 29-32, Mar. 1962. [44] G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, 2nd, Taiwan: Pearson Education, 2008. [45] H. T. Nguyen, D. Jung and H. Wang, “A 60GHz CMOS power amplifier with cascaded asymmetric distributed-active-transformer achieving watt-level peak output power with 20.8% PAE and supporting 2Gsym/s 64-QAM modulation,” in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019, pp. 90-92. [46] C. R. Chappidi, X. Wu and K. Sengupta, “Simultaneously broadband and back-off efficient mm-wave PAs: a multi-port network synthesis approach,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2543-2559, Sept. 2018. [47] C. R. Chappidi and K. Sengupta, “Frequency reconfigurable mm-wave power amplifier with active impedance synthesis in an asymmetrical non-isolated combiner: analysis and design,” in IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 1990-2008, Aug. 2017. [48] M. Vigilante and P. Reynaert, “A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS,” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 116-119. [49] S. Hu, F. Wang and H. Wang, “A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 32-33. [50] Keysight Technologies website: https://www.keysight.com. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73440 | - |
| dc.description.abstract | 本論文總共分成三大部分，第一部分是一個V頻段的疊接組態(cascode)功率放大器，使用65奈米互補式金屬氧化物半導體製程來設計。第二部分是一個Ka頻段的堆疊式(stack)功率放大器，也使用65奈米互補式金屬氧化物半導體製程來設計。最後一部分是一個K頻段且使用新的中和穩定技術(neutralization)的高輸出1dB功率壓縮點(OP1dB)共汲極功率放大器，使用90奈米互補式金屬氧化物半導體製程來設計。
在第一部分，提出了一個是V頻段的高功率、高效率且高增益的三級的功率放大器。一個新提出的疊接組態功率放大器被用來最佳化輸出級的大訊號特性。同時，使用了一個四路的輻射狀變壓功率結合器加上一條低阻抗傳輸線，因此功率放大器的輸出功率可以非常有效率的結合。此提出的V頻段功率放大器在60 GHz達到23.7 dBm的飽和輸出功率、22.1%的最大功率附加效率和29.7 dB的增益，晶片面積為0.653 mm^2。 在第二部分，提出了一個Ka頻段的高功率、高效率且小晶片面積的一級堆疊式功率放大器。為了要達到高輸出功率，使用堆疊三顆電晶體的技術。此外，利用了一個並聯在汲極和源極的回授電容來讓在堆疊三顆電晶體功率放大器裡的各個電晶體的汲極和源極之間的輸出電壓分配平均，因此不只提升了大訊號特性，也提升了長期可靠度。此提出的Ka頻段功率放大器在38 GHz達到24.8 dBm的飽和輸出功率、24.3%的最大功率附加效率和17.5 dB的增益，晶片面積為0.146 mm^2。 在最後一部分，提出了一個K頻段且使用新的中和穩定技術(neutralization)的高輸出1dB功率壓縮點(OP1dB)共汲極功率放大器。因為共汲極放大器高線性度的特性，此提出的共汲極功率放大器在K頻段可以達到高輸出1dB功率壓縮點(OP1dB)。此外，也引入一個新的共汲極放大器中和穩定技術(neutralization)來改善整體的穩定度和增益，所以此提出的互補式金屬氧化物半導體製程的共汲極功率放大器在所有互補式金屬氧化物半導體製程的共汲極功率放大器設計中可成功地第一次操作在高於10 GHz的地方。此提出的共汲極功率放大器在23 GHz達到22.9 dBm的飽和輸出功率、24.2%的最大功率附加效率、22.5 dBm的輸出1dB功率壓縮點(OP1dB)、22.5%的輸出1dB功率壓縮點(OP1dB)之附加效率和10.3 dB的增益，晶片面積為0.479 mm^2。 | zh_TW |
| dc.description.abstract | This thesis consists of three parts. The first part is a cascode power amplifier (PA) designed at V-band in 65-nm CMOS process. The second part is a stacked PA designed at Ka-band in 65-nm CMOS process. The last part is a K-band high OP1dB common-drain (CD) PA with new neutralization in 90-nm CMOS process.
In the first part, a V-band high output power, high efficiency and high power gain 3-stage PA is proposed. The introduced cascode amplifier is used to optimize the power performance of power stage. Meanwhile, a four-way radial transformer power combiner with a low impedance transmission line is adopted; hence the output power of the PA can be combined with remarkable efficiently. The proposed V-band PA achieves saturated output power of 23.7 dBm, peak power added efficiency (PAE) of 22.1% and power gain of 29.7 dB at 60 GHz with 0.653-mm^2 chip size. In the second part, a Ka-band one-stage stacked PA with high output power, high efficiency and small chip area is proposed. In order to achieve high output power, 3-stack technique is applied. Moreover, a shunt feedback drain-source capacitor is utilized to make the output voltage divide equally between drain and source of each individual transistor in three-stack PA, which enhances the power performance and the long-term reliability as well. The proposed Ka-band PA achieves saturated output power of 24.8 dBm, peak PAE of 24.3% and power gain of 17.5 dB at 38 GHz with 0.146-mm^2 chip size. In the last part, a K-band high OP1dB CD PA with new neutralization is proposed. Owing to high-linearity CD amplifier, the proposed CD PA can achieve high OP1dB at K-band. Furthermore, a new neutralization technique for the CD amplifier is introduced to improve overall stability and power gain as well so that the proposed CMOS CD PA can successfully operates above 10 GHz for the first time of the CMOS CD PA design. The proposed CD PA achieves saturated output power of 22.9 dBm, peak PAE of 24.2%, output 1-dB compression point (OP1dB) of 22.5 dBm with PAE of 22.5% and power gain of 10.3 dB at 23 GHz with 0.479-mm^2 chip size. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:35:01Z (GMT). No. of bitstreams: 1 ntu-108-R05942128-1.pdf: 7582975 bytes, checksum: 7673a273249a89b0121e91d063c800cc (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xviii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 2 1.2.1 K/Ka-band CMOS Power Amplifier 2 1.2.2 V-band CMOS Power Amplifier 4 1.2.3 Common-Drain CMOS Power Amplifier 6 1.3 Contributions 7 1.3.1 V-Band Cascode Power Amplifier 7 1.3.2 Ka-Band Three-Stack Power Amplifier 8 1.3.3 K-Band high-OP1dB Common-Drain Power Amplifier with New Neutralization Technique 9 1.4 Thesis Organization 9 Chapter 2 V-Band Power Amplifier with 23.7-dBm Output Power, 22.1% PAE and 29.7-dB Gain in 65-nm CMOS Process 11 2.1 Introduction 11 2.2 Transformer-Based Power-Combining Technique 13 2.2.1 Transformer-based Voltage Combining 13 2.2.2 Transformer-based Current Combining 14 2.3 Circuit Design 15 2.3.1 Circuit Architecture 15 2.3.2 Bias Selections and Device Design 18 2.3.3 Matching Networks 35 2.3.4 Circuit Schematic and Simulation Results 41 2.4 Experimental Results and Discussions 46 2.5 Summary 52 Chapter 3 Ka-Band Stacked Power Amplifier with 24.8-dBm Output Power and 24.3% PAE in 65-nm CMOS Process 53 3.1 Introduction 53 3.2 Circuit Design 54 3.2.1 Circuit Architecture 54 3.2.2 Bias Selections and Device Design 56 3.2.3 Matching Networks 76 3.2.4 Circuit Schematic and Simulation Results 78 3.3 Experimental Results and Discussions 82 3.4 Summary 86 Chapter 4 K-band High-OP1dB Common-Drain Power Amplifier with New Neutralization Technique in 90-nm CMOS 88 4.1 Introduction 88 4.1.1 Comparison with Three Basic Amplifiers 89 4.2 Circuit Design 90 4.2.1 Operation Principle [37], [40]-[42] 90 4.2.2 New Neutralization Technique 91 4.2.3 Circuit Architecture 94 4.2.4 Bias Selections and Device Design 95 4.2.5 Matching Networks 102 4.2.6 Circuit Schematic and Simulation Results 105 4.3 Experimental Results and Discussions 113 4.4 Summary 118 Chapter 5 Conclusion 119 REFERENCE 121 | |
| dc.language.iso | en | |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | 互補式金屬氧化物半導體 | zh_TW |
| dc.subject | K頻段 | zh_TW |
| dc.subject | Ka頻段 | zh_TW |
| dc.subject | V頻段 | zh_TW |
| dc.subject | CMOS | en |
| dc.subject | Power amplifier | en |
| dc.subject | K-band | en |
| dc.subject | Ka-band | en |
| dc.subject | V-band | en |
| dc.title | 毫米波高功率及高效率功率放大器之設計 | zh_TW |
| dc.title | Design of Millimeter-Wave High Output Power and High Efficiency Power Amplifiers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),蔡作敏(Zuo-Min Tsai),張鴻埜(Hong-Yeh Chang),蔡政翰 | |
| dc.subject.keyword | 互補式金屬氧化物半導體,功率放大器,K頻段,Ka頻段,V頻段, | zh_TW |
| dc.subject.keyword | CMOS,Power amplifier,K-band,Ka-band,V-band, | en |
| dc.relation.page | 127 | |
| dc.identifier.doi | 10.6342/NTU201900742 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-05-06 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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