請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73063完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳士元 | |
| dc.contributor.author | Tzu-Yu Hsia | en |
| dc.contributor.author | 夏紫瑀 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:15:55Z | - |
| dc.date.available | 2021-07-17 | |
| dc.date.copyright | 2019-07-17 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-15 | |
| dc.identifier.citation | [1] HANSEN R.C., “Phased Array Antennas,” Wiley Series in Microwave and Optical Engineering, ISBN: 9780471530763
[2] VISSER H.J., “Array and Phased Array Antenna Basics,” John Wiley & Sons, Ltd, ISBN: 9780470871171 [3] D.-W. Kang, H. D. Lee, C.-H. Kim, and S. Hong, “Ku-band MMIC phase shifter using a parallel resonator with 0.18-μm CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp. 294–301, Jan. 2006. [4] I.L. Abdalla, A. Allam, R. Pokharel, and H. Jia, “A DC-2.5GHz Voltage Variable Attenuator in 0.18-μm CMOS technology,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2014. [5] Chin Leong Lim, “Variable Attenuator Blends Dynamic Range, Linearity,” microwave & RF magazine, Feb. 2015. Available at https://www.mwrf.com/active-components/variable-attenuator-blends-dynamic-range-linearity [6] “TSMC 0.18-μm CMOS datasheet,”. Taiwan Semiconductor Manufactering. [7] “Agilent EEsoft ADS’s Manual” Agilent Technologies, Inc. [8] Sonnet software, Sonnet Software User’s Manual 14.52. [9] “Cadence Virtuoso Tutorial ver. 6.1,” University of Southern California, Oct 2015. [10] Kuo-Jung Sun, Zuo-Min Tsai, Kun-You Lin and Huei Wang, “A Noise Optimization Formulation for CMOS Low-Noise Amplifiers with On-Chip Low-Q Inductors,” IEEE TMTT, 4 April, 2006. [11] Muh-Dey Wei, Dirk Bormann, Stefan Kaehlert, Tobias D. Werth, Lei Liao, Sheng-Fuh Chang and Renato Negra, “3.5 GHz Triple Cascaded Current-Reuse Low Noise Amplifier,” NORCHIP, 2013. [12] Zaid Albataineh, Jafar Moheidat, and Yazan Hamada, “Design of High Gain 2.4GHz CMOS LNA Amplifier for Wireless Sensor Network Applications,” International Electrical and Electronics Engineering, 2017. [13] Yenheng Chen and Jengrern Yang“1 V UWB CG LNA at 3-8 GHz with Bulk-bias Method”, Information Science and Technology, 2013 [14] Chun Zhang, Zhihua Wang, “A low-power monolithic reconfigurable direct-conversion receiver RF front-end for 802.11a/b/g applications,” International Conference on Solid-State and Integrated-Circuit Technology, November, 2008. [15] K. Xuan, K.F. Tsang, W.C. Lee and S.C. Lee, “0.18 μm CMOS dual-band low-noise amplifier for ZigBee development,” Electronics Letters, January 2010. [16] Hau-Yiu Tsui and Jack Lau, “A 5GHz 56dB Voltage Gain 0.18μm CMOS LNA with Built-in Tunable Channel Filter for Direct Conversion 802.1 la Wireless LAN Receiver,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2003. [17] Hua-Chin Lee, Chao-Shiun Wang, and Chorng-Kuang Wang, “A 0.2–2.6 GHz Wideband Noise-Reduction Gm-Boosted LNA,” IEEE Microwave and Wireless Components (MWC) Letters, May 2012. [18] Chia-Lin Hsieh, Ming-Hang Wu, Jen-Hao Cheng, Jeng-Han Tsai and Tian-Wei Huang, “A 0.6-V 336-W 5-GHz LNA Using a Low-Voltage and Gain-Enhancement Architecture,” IEEE MTT-S International Microwave Symposium Digest (MTT), 2013. [19] F. Friis, “Noise Figure of Radio Receivers,” Proc. IRE, Vol. 32, pp.419-422, July 1944. [20] Akira Matsuzawa, “RF-SoC—Expectations and Required Conditions,” IEEE Transactions on Microwave Theory and Techniques (TMTT), January 2002. [21] Bon-Hyun Ku and Songcheol Hong, “6-bit CMOS Digital Attenuators with Low Phase Variations for X-Band Phased-Array Systems,” IEEE Transactions on Microwave Theory and Techniques (TMTT), July 2010. [22] Na Chen, “A Millimeter-wave 6-bit GaAs Monolithic Digital Attenuator with Low Insertion Phase Shift,” International Workshop on Microwave and Millimeter Wave Circuits and System Technology, 2013. [23] Yong-Sheng Dai, Da-Gang Fang, and Yong-Xin Guo, “A Novel UWB (0.045–50 GHz) Digital/Analog Compatible MMIC Variable Attenuator with Low Insertion Phase Shift and Large Dynamic Range,” IEEE Microwave and Wireless Components Letters (MWCL), VOL. 17, NO. 1, JANUARY 2007. [24] Arash Ebrahimi Jarihani, Fatih Kocer, “A Phase Coherent 7-bit Digital Step Attenuator on 0.18μm SOI,” European Microwave Integrated Circuits Conference (EuMIC), Oct. 2017. [25] I.L. Abdalla, A.Allam, R. Pokharel and H. Jia, “A DC-2.5GHz Voltage Variable Attenuator in 0.18-μm CMOS Technology,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2014. [26] Chang-Tsung Fu, Chun-Lin Ko, and Chien-Nan Kuo, “A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multistandard Wireless Receiver,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, July 2007. [27] Oleg Stukach, Arman Mirmanov and Yuriy Yu. Ivanov, “The Factor and Regression Characterization of the Broad-band Variable Attenuator with Large Dynamic Range and Low Insertion Phase Shift,” Moscow Workshop on Electronic and Networking Technologies (MWENT), 2018. [28] A. Slimane, A. Taibi, A. A. Saadi, D. Maafri, S. Tedjini, S. Traiche, “A 0.6 V, 2.1 mW CMOS UWB LNA for 3-5 GHz Wireless Receivers,” International Midwest Symposium on Circuits and Systems (MWSCAS), Oct. 2016. [29] Rahul Singh1, Greg Slovin1, Min Xu, Ahmad Khairi, Sandipan Kundu, T.E. Schlesinger, James A. Bain1 and Jeyanandh Paramesh1, “A 3/5 GHz Reconfigurable CMOS Low-Noise Amplifier Integrated with a Four-Terminal Phase-Change RF Switch,” IEEE International Electron Devices Meeting (IEDM), Dec. 2015. [30] H.-M. Hsu, J.-Y. Chang, J.-G. Su, C.-C. Tsai, S.-C.Wong, C. W. Chen, K. R. Peng, S. P. Ma, C. H. Chen, T. H. Yeh, C. H. Lin, Y. C. Sun, and C. Y. Chang, “A 0.18-μm foundry RF CMOS technology with 70-GHz f_T for single chip system solutions,” in IEEE MTT-S Int. Microw. Symp. Dig., 2001, pp. 1869–1872. [31] Shashank Tiwari, Venkata Narayana Rao Vanukuru, and Jayanta Mukherjee Noise, “Figure Analysis of 2.5 GHz Folded Cascode LNA using High-Q Layout Optimized Inductors,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2015. [32] Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3–5-GHz UWB System,” IEEE Journal of Solid-State Circuits, VOL. 40, NO. 2, FEBRUARY 2005. [33] Ickhyun Song, Moon-Kyu Cho and John D. Cressler, “Design and Analysis of a Low Loss, Wideband Digital Step Attenuator with Minimized Amplitude and Phase Variations,” IEEE Journal of Solid-State Circuits, VOL. 53, NO. 8, AUGUST 2018. [34] Babak Ansari, Hossein Shamsi, Ali Shahhoseini, “Analysis of a 3-5 GHz UWB CMOS Low-Noise Amplifier for Wireless Applications,” IEEE International Midwest Symposium on Circuits and Systems, Aug. 2009. [35] Yu-Jun Hong, San-Fu Wang, Po-Tsung Chen, Yuh-Shyan Hwang and Jiann-Jong Chen, “A Concurrent Dual-Band 2.4/5.2 GHz Low-Noise Amplifier Using Gain Enhanced Techniques,” Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), May 2015. [36] A. Papadimitriou, M. Bucher, “Optimization of RF Low Noise Amplifier Design Using Analytical Model and Genetic Computation,” Mixed Design of Integrated Circuits and Systems, June 2017. [37] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits, 2nd Edition,” Cambridge Univ. Press. Cambridge U.K, 2004. [38] Yan-Yu Huang, “CMOS-Based Amplitude and Phase Control Circuits Designed for Multi-Standard Wireless Communication Systems,” Degree Doctor of Philosophy in the School of Electrical and Computer Engineering of Georgia Institute of Technology, August 2011. [39] W.-C. Huang, C.-C. Chiong and H. Wang, “A Fully-Integrated S-Band Differential LNA in 0.15-μm GaAs pHEMT for Radio Astronomical Receiver,” IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2018. [40] Jing Zhao, Bo Zhang, and Xiaofeng Yang, “A 25–30 GHz 6-bit digital attenuator with high accuracy and low insertion loss,” IEEE MTT-S International Wireless Symposium (IWS), March 2016. [41] Yong-Sheng Dai, Ping Li, Qun-Fei Han, Shao-Bo Chen, Xi Chen, Li-Jie Wang, Li Xu, and Ri-Qing Chen, “Research on a novel 2∼18 GHz PHEMT MMIC digital attenuator with low insertion phase shift,” International Conference on Microwave and Millimeter Wave Technology (ICMMT), July 2012. [42] I. Gil, I. Cairo, and J.J. Sieiro, “Low-power single-to-differential LNA at S-band based on optimised transformer topology and integrated ESD,” Electronics Letters, January 2008. [43] Johannes Sturm, Suchendranath Popuri, and Xinbo Xiang, “CMOS noise canceling balun LNA with tunable bandpass from 4.6 GHz to 5.8 GHz,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2014. [44] M. Khurram, and S.M.Rezaul Hasan, “Series peaked noise matched gm-boosted 3.1–10.6 GHz CG CMOS differential LNA for UWB WiMedia,” Electronics Letters, November 2011. [45] “Three and Four Port S-parameter Measurements, Anritsu Network Measurement System Application Note,” Anritsu Company, 2001. [46] 楊博凱撰，以0.18微米互補式金氧半製程實現高精確度且低損耗之差動饋入數位衰減器，國立臺灣大學電信工程研究所碩士論文，2018. [47] 李祐棠撰，應用於毫米波波段之砷化鎵低雜訊放大器之設計與毫米波發射器元件與系統構裝之研究，國立臺灣大學電信工程研究所碩士論文，2015. [48] Hung-Ting Chou, Zhi-Lin Ke, Hwann-Kaeo Chiou, “A Low Power Compact Size Forward Body-Biased K-Band CMOS Low Noise Amplifier,” Asia-Pacific Microwave Conference (APMC), 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73063 | - |
| dc.description.abstract | 本論文以0.18微米互補式金氧半製程實現應用於S頻段差動饋入接收機系統之低雜訊放大器和數位衰減器，包含其電路設計與量測，以及接收器系統的整合。
首先是S頻段差動饋入之低雜訊放大器，操作頻率範圍為3.1至3.5 GHz，論文主要貢獻在於設計小尺寸但高增益的低雜訊放大器，因此設計兩級但增益仍達近18 dB，且在電路佈局中將兩個電感環繞在一起以節省面積。 接著是差動饋入數位衰減器，論文主要貢獻在於提出一種創新的架構，不同點為其設計的級間電路本身包含一個差動放大器以及緩衝放大器，此級間電路具有消除各級之間阻抗影響的功能，使數位衰減器各級間的衰減量互不影響，進而提升衰減器的精確度，並且此架構能降低衰減器的介入損耗。 最後則是S頻段(3.1到3.5 GHz)差動饋入接收機的系統整合，各元件間的級間電路亦是採用差動放大器加上緩衝放大器之架構去消除阻抗不匹配的影響，各元件在級間電路的隔離下皆能正常工作，接收機的輸出功率亦是本篇論文重要的指標，然而一些元件的介入損耗太大以及其1 dB增益壓縮時的輸入功率(IP1dB)不足，均使接收機的輸出功率過小，而未能滿足設計目標。 | zh_TW |
| dc.description.abstract | In this thesis, we demonstrate the design and measurement results of a low noise am-plifier (LNA) and digital attenuators applied to a S-band receiver with differential feed using 0.18-μm CMOS process. Furthermore, the integration of the receiver system is also demonstrated.
First, for the S-band differentially-fed low noise amplifier, the targeted operating frequency range is from 3.1 to 3.5 GHz. The main contribution of this thesis lies in de-signing the LNA with high gain while keeping a small chip size. A two-stage design of the LNA with nearly 18-dB gain is demonstrated, and a special layout technique is used by surrounding two individual inductors together to save die area. As for the differentially-fed digital attenuators, the contribution of this thesis lies in the novel structure of the inter-stage circuit we proposed. The difference of the inter-stage circuit is that it is composed of a differential amplifier and buffer amplifiers. The in-ter-stage circuit can eliminate the impedance influence caused by adjacent circuits so that the attenuation level of each stages do not affect each other, and thus the attenuator’s ac-curacy is enhanced. Also, this structure could lower the attenuator’s insertion loss. Lastly, for the integration of the S-band (3.1 to 3.5 GHz) differentially-fed receiver system. A differential amplifier subjoining buffer amplifiers is also used as inter-stage cir-cuits to remove the impedance mismatch. All the units can work properly thanks to the high isolation of inter-stage circuits. While the output power of the receiver is also an im-portant indicator, the large insertion loss and poor IP1dB due to some other components render the output power of the receiver system too small to meet our design goal. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:15:55Z (GMT). No. of bitstreams: 1 ntu-108-R05942149-1.pdf: 7766985 bytes, checksum: 4d005867aa23fcb839b2050303dafa03 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES xii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 3 1.2.1 LNAs around S-band 3 1.2.2 Digital Attenuator 6 1.3 Contributions 8 1.4 Thesis Organization 8 Chapter 2 Design of a S-band LNA 10 2.1 Circuit Design of the S-band LNA 10 2.1.1 Device Selection 10 2.1.2 Design of Input Matching Network 14 2.1.3 Circuit Design 18 2.2 Experimental Results 29 2.3 Summary 35 Chapter 3 Design of Digital Attenuators 37 3.1 Circuit Design of the Digital Attenuator 37 3.1.1 Structure of Digital Attenuation Unit 37 3.1.2 Design of Inter-Stage Matching Network 43 3.1.3 Full Circuit Design 50 3.2 Simulation Results 52 3.2.1 RFA/MA0 52 3.2.2 6-bit ATT/MA1 62 3.3 Experiment Results 72 3.4 Summary 79 Chapter 4 Receiver Integration of S-band Radar RF-SoC Using CMOS Technology 82 4.1 Introduction 82 4.2 Receiver Architecture 83 4.3 Simulation results 84 4.3.1 LNA, RFA and Mixer1 88 4.3.2 6-bit ATT, DA1, 6-bit PS, 5-bit PS and BA10dB 91 4.3.3 Output Power 95 4.4 Summary 100 Chapter 5 Conclusions and Future Work 102 5.1 Conclusions 102 5.2 Future Work 102 References 105 | |
| dc.language.iso | zh-TW | |
| dc.title | 以0.18微米互補式金氧半製程設計應用於S頻段雷達射頻系統單晶片之差動饋入低雜訊放大器與數位衰減器 | zh_TW |
| dc.title | Design of Differentially-Fed Low Noise Amplifier and Digital Attenuators for S-Band Radar RF-SoC Using 0.18-μm CMOS Process | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡作敏,歐陽良昱 | |
| dc.subject.keyword | 低雜訊放大器,S-band,數位衰減器,差動饋入,接收器,金氧半場效電晶體, | zh_TW |
| dc.subject.keyword | CMOS,digital attenuator,low noise amplifier (LNA),RF-SoC, | en |
| dc.relation.page | 111 | |
| dc.identifier.doi | 10.6342/NTU201901453 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-108-1.pdf 目前未授權公開取用 | 7.58 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。