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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模 | |
dc.contributor.author | Ming-Ting Lee | en |
dc.contributor.author | 李明庭 | zh_TW |
dc.date.accessioned | 2021-06-17T07:11:32Z | - |
dc.date.available | 2020-08-07 | |
dc.date.copyright | 2019-08-07 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-07-19 | |
dc.identifier.citation | [Breuer 05] Breuer, Melvin A. 'Multi-media applications and imprecise computation.'
8th IEEE Euromicro Conference on Digital System Design (pp. 2-7) 2005. [Chang 17] Chang, Chih-Ming, et al. 'Test Pattern Compression for Probabilistic Circuits.' 26th IEEE Asian Test Symposium (pp. 23-27) 2007. [Cheemalavagu 05] Cheemalavagu, Suresh, et al. 'A probabilistic CMOS switch and its realization by exploiting noise.' IFIP International Conference on VLSI. 2005. [Han 05] Han, Jie, et al. 'Faults, error bounds and reliability of nanoelectronic circuits.' IEEE International Conference on Application-Specific Systems, Architecture Processors 2005. [Google 18] A preview of Bristlecone, Google’s New Quantum Processor. https://ai.googleblog.com/2018/03/a-preview-of-bristlecone-googles-new.html [Han 11] Han, Jie, et al. 'Reliability evaluation of logic circuits using probabilistic gate models.' Microelectronics Reliability 51.2 (pp. 468-476) 2011. [Hayes 04] Hayes, John P., Ilia Polian, and Bernd Becker. 'Testing for missing-gate faults in reversible circuits.' 13th IEEE Asian Test Symposium. 2004. [ITES 01] International Technology Roadmap for Semiconductors (ITRS), 2001. https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2001/1_Executive%20Summary.pdf [Kim 14] Kim, J., & Tiwari, S. “Inexact computing using probabilistic circuits: Ultra low-power digital processing,” ACM Journal on Emerging Technologies in Computing Systems (JETC). 2014. [Krishnaswamy 07] Krishnaswamy, Smita, Igor L. Markov, and John P. Hayes. 'Tracking uncertainty with probabilistic logic circuit testing.' IEEE Design & Test of Computers 24.4. (pp. 312-321) 2007. [Ladd 10] Ladd, Thaddeus D., et al. 'Quantum computers.' Nature464.7285 2010. [Lehmann 97] Lehmann, E. L., & Romano, J. P. Testing statistical hypotheses. Springer Science & Business Media 2006. [MathBits web] Understanding Z-scores. https://mathbitsnotebook.com/Algebra2/Statistics/STzScores.html [McCluskey 00] McCluskey, Edward J., and Chao-Wen Tseng. 'Stuck-fault tests vs. actual defects.' Proceedings IEEE International Test Conference 2000. [Monroe 14] Monroe, C., et al. 'Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects.' Physical Review A 89.2. 2014. [NanGate 08] NanGate Open Cell Library. Retrieved from http://www.nangate.com/, 2008. [Patel 03] Patel, Ketan N., Igor L. Markov, and John P. Hayes. 'Evaluating circuit reliability under probabilistic gate-level fault models.' Proceedings of the International Workshop on Logic and Synthesis. 2003. [Palem 12] Palem, K., & Lingamneni, A. (2012, June). Palem, Krishna, and Avinash Lingamneni. 'What to do about the end of Moore's law, probably!.' IEEE/ACM DAC Design Automation Conference 2012. [Paler 11] Paler, Alexandru, et al. 'Tomographic testing and validation of probabilistic circuits.' 16th IEEE European Test Symposium 2011. [Rancher 03] Rencher, A. C. Methods of multivariate analysis (Vol. 492). John Wiley & Sons 2003. [Stick 06] Stick, Dan, et al. 'Ion trap in a semiconductor chip.' Nature Physics 2.1 2006. [Yang 19] Kai-Chieh Yang, et al. “ATPG and Test Compression for Probabilistic Circuits.” IEEE VLSI Design, Automation and Test (VLSI-DAT) 2019. [Zscorecalculator web] Z-score Calculator. https://www.zscorecalculator.com/ | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72952 | - |
dc.description.abstract | 機率電路是一種極低功耗電路設計的未來走向,機率電路可以在正確率以及功耗當中做出良好的取捨,尤其適合用在一些能容錯的應用像是影像處理以及機器學習。然而機率電路的行為模式比傳統電路來得更加複雜,因為前者在給定相同的輸入圖樣下,有可能會產生不同的輸出結果,我們需要重複很多次測試才能獲得一個輸出的機率分布來描述機率電路,在這篇論文當中,我們提出了一個測試方法特別針對具有機率行為的電路,我們使用了多變數假設檢定來減少測試圖樣的重複次數,我們同時也使用斷層測試來判斷一個接受測試電路的好壞藉此達成減少誤宰的情形,實驗結果顯示我們的總測試圖樣長度比過去技術平均少了82%的長度,我們的誤宰機率也比過去技術平均減少了99%。 | zh_TW |
dc.description.abstract | Probabilistic circuits are a potential solution for low power designs which trade off correctness for power consumption. Probabilistic circuits are especially suitable for error-tolerant applications such as video processing or machine learning. The behavior of probabilistic circuits is more complicated than deterministic circuits because the former produce different outputs given the same inputs. Quantum circuits are sols inherently probabilistic circuits. When testing, we need to apply test patterns many times to obtain output distribution of probabilistic circuits. In this thesis, we propose a test flow targeting circuits with probabilistic behavior. When testing, we apply multivariate hypothesis testing to reduce pattern repetition. We also reduce overkill by tomographic testing to determine pass or fail of circuit under test (CUT). Experimental results show that our proposed technique can reduce pattern repetition by 82% and reduce overkill by 99% than a previous work. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T07:11:32Z (GMT). No. of bitstreams: 1 ntu-108-R06943147-1.pdf: 2069235 bytes, checksum: 80b0b11c05d87dec68533b471aacb50e (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 致謝 I
摘要 II ABSTRACT III TABLE OF CONTENTS IV LIST OF FIGURES VI LIST OF TABLES VII CHAPTER 1. INTRODUCTION 1 1.1 MOTIVATION 1 1.2 PROPOSED TECHNIQUE 5 1.3 ASSUMPTION 7 1.4 CONTRIBUTION 7 1.5 ORGANIZATION 8 CHAPTER 2. BACKGROUND 9 2.1 PROBABILISTIC GATE MODEL (PGM) 9 2.2 FAULTY PROBABILISTIC GATE MODEL 11 2.3 HYPOTHESIS TESTING 13 2.3.1 Introduction of Hypothesis Testing 13 2.3.2 Z-Score 14 2.3.3 Mahalanobis distance 17 2.3.4 Chi-squared distribution 17 2.3.5 Critical value 20 2.4 HYPOTHESIS TESTING FOR PROBABILISTIC CIRCUITS 22 2.5 PREVIOUS WORK ABOUT PROBABILISTIC CIRCUITS 24 CHAPTER 3. PROPOSED TECHNIQUES 30 3.1 OVERALL FLOW 30 3.2 MULTIVARIATE HYPOTHESIS TESTING 32 3.3 TOMOGRAPHIC TESTING 34 3.4 ABORT HARD-TO-FAULT 39 CHAPTER 4. EXPERIMENTAL RESULTS 41 4.1 EXPERIMENTAL PARAMETER SETTING AND BENCHMARK 42 4.2 PATTERN REPETITION COMPARISON 45 4.3 OVERKILL AND FAULT COVERAGE LOSS 45 CHAPTER 5. DISCUSSION 49 CHAPTER 6. CONCLUSION 52 REFERENCE 53 | |
dc.language.iso | en | |
dc.title | 針對機率電路之高效率且低誤宰測試 | zh_TW |
dc.title | High Efficiency and Low Overkill Testing for Probabilistic Circuits | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江介宏,郭斯彥 | |
dc.subject.keyword | 機率電路,測試圖樣壓縮, | zh_TW |
dc.subject.keyword | Probabilistic Circuit,Test Pattern Compression, | en |
dc.relation.page | 55 | |
dc.identifier.doi | 10.6342/NTU201901586 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-07-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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