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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | |
| dc.contributor.author | Li-Yuan Hsu | en |
| dc.contributor.author | 許力元 | zh_TW |
| dc.date.accessioned | 2021-05-19T17:40:54Z | - |
| dc.date.available | 2024-07-31 | |
| dc.date.available | 2021-05-19T17:40:54Z | - |
| dc.date.copyright | 2019-07-31 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-29 | |
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Takahashi, Hao San and Nobukazu Takai, 'SAR ADC algorithm with redundancy,' APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 2008, pp. 268-271. [32]P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3rd ed. New York: Oxford University Press, 2008, pp. 444. [33]K. Sun, G. Wang, Q. Zhang, S. Elahmadi and P. Gui, 'A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 821-833, March 2019. [34]L. Kull et al., 'A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET,' in IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3508-3516, Dec. 2018. [35]T. Ali et al., '6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology,' 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 118-120. 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Beidas, 'A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction,' Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, 2012, pp. 1-4. [42]D. Luu et al., 'A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C276-C277. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7278 | - |
| dc.description.abstract | 本論文提出一個應用於逐漸趨近式類比至數位轉換器的電路設計技術，並且基於所提出的技術，實現一個使用九十奈米製程的單通道十位元每秒取樣二億次的非同步逐漸趨近式類比至數位轉換器。該技術為雙迴路非同步控制，其大幅降低因傳統非同步控制架構的現在，在最低有效位元階段造成時間浪費的問題，提升操作速度。
本設計使用台積電 90-nm UTM CMOS製程來實作晶片，其核心的電路面積為 192 µm × 115 µm。佈局後模擬結果顯示，此設計在0.9伏特的電壓與每秒取樣二億取樣的操作速度下，總消耗功率為1.61 mW，有效位元數為9.26 bits，每次資料轉換所消耗的能量為13fJ。預估最大DNL與INL的一個標準差分別為0.298LSB與0.35 LSB。 本次設計已於2019/07/10下線，目前正在製作階段。排定於2019/09/26晶片製作完成 | zh_TW |
| dc.description.abstract | This thesis proposes a control architecture for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 200-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed architecture. The proposed architecture is a dual-loop asynchronous control scheme. It reduce the waste time problem in LSB steps, which result from the architectural limitation of a conventional asynchronous control. Therefore, increase the speed.
The physical design was implement in TSMC 90-nm CMOS process. The core area is 115 µm × 192 µm. From post-layout simulation, at 0.9 V supply voltage and 200-MS/s sampling rate, the total power consumption is 1.61 mW, and ENOB is 9.26 bits. The prediction of maximum 1-sigma DNL and INL are 0.298 LSB and 0.35 LSB respectively This design is in fabrication process and was taped out at 2019/07/10。The chip out was scheduled to 2019/09/26. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-19T17:40:54Z (GMT). No. of bitstreams: 1 ntu-108-R03943118-1.pdf: 6318674 bytes, checksum: 506b4f1606a2d99cfcf15d8c748abdfc (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | Chapter 1Introduction1
1.1Motivation1 1.2Thesis Organization4 Chapter 2Fundamentals of Analog-to-Digital Conversion5 2.1Introduction5 2.1.1Sampling5 2.1.2Quantization8 2.2Static Specifications10 2.2.1Offset Error11 2.2.2Gain error12 2.2.3Differential Non-linearity (DNL)13 2.2.4Integral Non-linearity (INL)14 2.2.5Missing code16 2.2.6Non-monotonic16 2.3Dynamic specifications17 2.3.1Signal-to-noise ratio (SNR)18 2.3.2Total harmonic distortion (THD),19 2.3.3Effective number-of-bits (ENOB)19 2.3.4Signal-to-noise and distortion ratio (SNDR)20 2.3.5Spurious-free dynamic range (SFDR)20 2.3.6Effective resolution (ER)20 2.3.7Effective resolution bandwidth (ERBW)20 Chapter 3High-Speed Design Considerations of Single-Channel SAR ADC21 3.1Introduction21 3.2Operations of SAR ADC23 3.3Settling time of capacitive-DAC25 Chapter 4A 10-Bit 200-MS/s SAR ADC31 4.1Introduction31 4.2Proposed dual-loop asynchronous control34 4.3Architecture of the proposed SAR ADC38 4.4Circuit implementation39 4.4.1Bootstrapped Switch39 4.4.2Three-stage dynamic comparator40 4.4.3Latch SAR logic41 4.4.4DAC41 4.4.5Decoder42 4.4.6Sampling clock generator42 Chapter 5Post-Layout Simulations43 Chapter 6Measurement Considerations51 6.1Noise coupling in the proposed ADC51 6.1.1Substrate noise51 6.1.2Power supply noise53 6.1.3Signal crosstalk55 6.2Design for noise coupling suppression55 6.3Chip floor plan and layout59 6.4Full-chip simulation and performance prediction61 Chapter 7Conclusions66 REFERENCES68 | |
| dc.language.iso | en | |
| dc.title | 一個以雙迴路非同步控制之九十奈米十位元每秒取樣二億次的逐漸趨近式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit 200-MS/s SAR ADC with Dual-loop Asynchronous Control in 90nm CMOS | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張順志,鍾勇輝,趙昌博,曹恆偉 | |
| dc.subject.keyword | 高速,非同步控制,逐漸趨近式,類比至數位轉換器, | zh_TW |
| dc.subject.keyword | high-speed,asynchronous control,successive approximation,analog-to-digital converter, | en |
| dc.relation.page | 73 | |
| dc.identifier.doi | 10.6342/NTU201902051 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2019-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2024-07-31 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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