具穩定鎖定鎖頻迴路之次取樣鎖相迴路設計

Abstract

次取樣 (sub-sampling)技巧近年來常被用於鎖相迴路當中，此技巧能有效降低其頻寬內相位雜訊，因此能將頻寬變寬，得到更低的方均根抖動，然而次取樣迴路的偵測頻率範圍很窄，因此需要額外的鎖頻迴(FLL) 來偵測較大的頻率偏差並進行校正。在使用傳統鎖頻迴路下，當鎖相迴路脫鎖時，會需要很長的鎖定時間，這在許多系統應用下是不被允許的。 本論文實現了一個整數型鎖相迴路，主架構採用次取樣技巧，以降低頻寬內雜訊，另外也使用本論文提出的鎖頻迴路，使得鎖相迴路更加穩定。此鎖相迴路使用TSMC 90-nm CMOS製程實現，核心電路面積為0.3 mm2，整個電路操作於1.2 V，輸出頻率範圍為2.22-2.48 GHz。當輸入參考頻率為20 MHz，輸出頻率為2.42 GHz時，頻寬內相位雜訊為-110 dBc/Hz，在頻率偏移1 kHz至30 MHz內的積分方均根抖動 (RMS Jitter) 為539.3 fs，參考突波 (reference spur) 為-50 dBc，功耗為14.6 mW。當輸出頻率從2.4 GHz切換至2.46 GHz的鎖定時間大約為3.2 μs。

Sub-sampling technique has been adopted in the PLL to reduce in-band phase noise nowadays. Hence, the loop bandwidth can be expanded to reduce the RMS jitter furthermore. However, the sub-sampling loop (SSL) can not detect large frequency. It needs an additional frequency-locked loop (FLL) to calibrate frequency. Nevertheless, if the PLL loses lock by some reasons, it needs a long locking time while using the traditional FLL. This thesis implements an integer-N PLL, which can achieve low in-band phase noise by the sub-sampling technique. In addition, the proposed frequency-locked loop (FLL) makes the PLL more robust. This PLL is fabricated in 90-nm CMOS technology. The active area is 0.3 mm2. The power supply is 1.2 V. The output frequency ranges from 2.22 to 2.48 GHz. From the measurement results, the in-band phase noise is -110 dBc/Hz, the RMS jitter integrated from 10 kHz to 30 MHz frequency deviation is 539.3 fs, the reference spur is -50 dBc. The power consumption is 14.6 mW at 2.42-GHz output frequency with 20-MHz input reference frequency. While switching the output frequency from 2.4 to 2.46 GHz, the locking time is about 3.2 μs。