請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72458完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪一薰 | |
| dc.contributor.author | Hung-Chun Wu | en |
| dc.contributor.author | 吳泓均 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:59:26Z | - |
| dc.date.available | 2024-08-13 | |
| dc.date.copyright | 2019-08-13 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-05 | |
| dc.identifier.citation | 參考文獻
[1] G.E. Moore, Cramming more components onto integrated circuits, McGraw-Hill New York, NY, USA:, 1965. [2] A. Paul, Intel's 10nm Is Broken, Delayed Until 2019, Tom's Hardware, 2018. [3] K. Jeff, Intel outlines its struggles with 10-nm chip production, The Tech Report-PC Hardware Explored, 2018. [4] M. Töpper, T. Baumgartner, M. Klein, T. Fritzsch, J. Roeder, M. Lutz, M. Von Suchodoletz, H. Oppermann, H. Reichl, Low cost wafer-level 3-D integration without TSV, Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, IEEE, 2009, pp. 339-344. [5] T. Fritzsch, R. Mrossko, T. Baumgartner, M. Toepper, M. Klein, J. Wolf, B. Wunderle, H. Reichl, 3-D thin chip integration technology-from technology development to application, 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, IEEE, 2009, pp. 1-8. [6] J.-C. Souriau, O. Lignier, M. Charrier, G. Poupon, Wafer level processing of 3D system in package for RF and data application, Electronic Components and Technology Conference, 2005. Proceedings. 55th, IEEE, 2005, pp. 356-361. [7] V. Eveloy, S. Ganesan, Y. Fukuda, J. Wu, M.G. Pecht, WEEE, RoHS, and what you must do to get ready for lead-free electronics, 2005 6th International Conference on Electronic Packaging Technology, IEEE, 2005, pp. 27-44. [8] M.A. Ashworth, G.D. Wilcox, R.L. Higginson, R.J. Heath, C. Liu, R.J. Mortimer, The effect of electroplating parameters and substrate material on tin whisker formation, Microelectronics Reliability 55(1) (2015) 180-191. [9] S.L. Tay, A.S.M.A. Haseeb, M.R. Johan, P.R. Munroe, M.Z. Quadir, Influence of Ni nanoparticle on the morphology and growth of interfacial intermetallic compounds between Sn–3.8Ag–0.7Cu lead-free solder and copper substrate, Intermetallics 33(33) (2013) 8-15. [10] K.K. Xiang, A.S.M.A. Haseeb, M.M. Arafat, G. Yingxin, Effects of Mn nanoparticles on wettability and intermetallic compounds in between Sn-3.8Ag-0.7Cu and Cu substrate during multiple reflow, Asia Symposium on Quality Electronic Design, Asqed, 2012, pp. 297 - 301. [11] Z. Moser, P. Sebo, W. Gąsior, P. Svec, J. Pstruś, Effect of indium on wettability of Sn–Ag–Cu solders. Experiment vs. modeling, Part I, Calphad-computer Coupling of Phase Diagrams & Thermochemistry 33(1) (2009) 63-68. [12] H.B. Sang, Y.L. Sang, H.Y. Kim, S. Im, Comparison of the optical properties of ZnO thin films grown on various substrates by pulsed laser deposition, Applied Surface Science 168(s 1–4) (2000) 332–334. [13] K. Vanheusden, C.H. Seager, W.L. Warren, D.R. Tallant, Correlation between photoluminescence and oxygen vacancies in ZnO phosphors, Applied Physics Letters 68(3) (1996) 403-405. [14] H.S. Kang, J.S. Kang, S.S. Pang, Variation of light emitting properties of ZnO thin films depending on post-annealing temperature, Materials Science & Engineering B 102(1) (2003) 313-316. [15] J. Wu, S.-b. Xue, J.-w. Wang, S. Liu, Y.-l. Han, L.-j. Wang, Recent progress of Sn–Ag–Cu lead-free solders bearing alloy elements and nanoparticles in electronic packaging, Journal of Materials Science: Materials in Electronics 27(12) (2016) 12729-12763. [16] W. Dong, Y. Shi, Y. Lei, Z. Xia, F. Guo, Effects of small amounts of Ni/P/Ce element additions on the microstructure and properties of Sn3.0Ag0.5Cu solder alloy, Journal of Materials Science Materials in Electronics 20(10) (2008) 1008-1017. [17] Y. Shi, J. Tian, H. Hao, Z. Xia, Y. Lei, F. Guo, Effects of small amount addition of rare earth Er on microstructure and property of SnAgCu solder, Journal of Alloys & Compounds 453(1–2) (2008) 180-184. [18] L. Gao, S. Xue, L. Zhang, Z. Xiao, W. Dai, F. Ji, H. Ye, G. Zeng, Effect of praseodymium on the microstructure and properties of Sn3.8Ag0.7Cu solder, Journal of Materials Science Materials in Electronics 21(9) (2010) 910-916. [19] H. Hao, J. Tian, Y.W. Shi, Y.P. Lei, Z.D. Xia, Properties of Sn3.8Ag0.7Cu Solder Alloy with Trace Rare Earth Element Y Additions, Journal of Electronic Materials 36(36) (2007) 766-774. [20] B. Li, Y. Shi, Y. Lei, F. Guo, Z. Xia, B. Zong, Effect of rare earth element addition on the microstructure of Sn-Ag-Cu solder joint, Journal of Electronic Materials 34(3) (2005) 217-224. [21] L. Gao, S. Xue, L. Zhang, Z. Sheng, G. Zeng, F. Ji, Effects of trace rare earth Nd addition on microstructure and properties of SnAgCu solder, Journal of Materials Science Materials in Electronics 21(7) (2010) 643-648. [22] M.A. Dudek, N. Chawla, Mechanisms for Sn whisker growth in rare earth-containing Pb-free solders, Acta Materialia 57(15) (2009) 4588-4599. [23] H. Fallahi, M.S. Nurulakmal, A.F. Arezodar, J. Abdullah, Effect of iron and indium on IMC formation and mechanical properties of lead-free solder, Materials Science & Engineering A 553(38) (2012) 22-31. [24] K.M. Kumar, V. Kripesh, L. Shen, A.A. Tay, Study on the microstructure and mechanical properties of a novel SWCNT-reinforced solder alloy for ultra-fine pitch applications, Thin Solid Films 504(1-2) (2006) 371-378. [25] K.M. Kumar, V. Kripesh, A.A. Tay, Single-wall carbon nanotube (SWCNT) functionalized Sn–Ag–Cu lead-free composite solders, Journal of Alloys and Compounds 450(1-2) (2008) 229-237. [26] X.D. Liu, Y.D. Han, H.Y. Jing, J. Wei, L.Y. Xu, Effect of graphene nanosheets reinforcement on the performance of SnAgCu lead-free solder, Lecture Notes in Computer Science 562(562) (2013) 25-32. [27] K.-C. Chen, W.-W. Wu, C.-N. Liao, L.-J. Chen, K. Tu, Observation of atomic diffusion at twin-modified grain boundaries in copper, Science 321(5892) (2008) 1066-1069. [28] H.-Y. Hsiao, C.-M. Liu, H.-w. Lin, T.-C. Liu, C.-L. Lu, Y.-S. Huang, C. Chen, K. Tu, Unidirectional growth of microbumps on (111)-oriented and nanotwinned copper, Science 336(6084) (2012) 1007-1010. [29] W.J. Abernathy, J.M. Utterback, Patterns of industrial innovation, Technology review 80(7) (1978) 40-47. [30] R.E. Gomory, R.W. Schmitt, Science and product, Science 240(4856) (1988) 1131-1204. [31] M. Tushman, D. Nadler, Organizing for innovation, California management review 28(3) (1986) 74-92. [32] G. Dosi, Technological paradigms and technological trajectories: a suggested interpretation of the determinants and directions of technical change, Research policy 11(3) (1982) 147-162. [33] M. Sakakibara, Heterogeneity of firm capabilities and cooperative research and development: an empirical examination of motives, Strategic management journal 18(S1) (1997) 143-164. [34] B.B. Tyler, H. Kevin Steensma, Evaluating technological collaborative opportunities: A cognitive modeling perspective, Strategic Management Journal 16(S1) (1995) 43-70. [35] J. Tidd, M.J. Trewhella, Organizational and technological antecedents for knowledge acquisition and learning, R&D Management 27(4) (1997) 359-375. [36] E.W. Tsang, Strategies for transferring technology to China, Long Range Planning 27(3) (1994) 98-107. [37] W.M. Cohen, D.A. Levinthal, Absorptive capacity: A new perspective on learning and innovation, Administrative science quarterly 35(1) (1990) 128-152. [38] J.Z. Yin, Technological capabilities as determinants of the success of technology transfer projects, Technological forecasting and social change 42(1) (1992) 17-29. [39] A. Brandenburger, B. Nalebuff, Co-opetition, Crown Business1998. [40] M. Bengtsson, S. Kock, ” Coopetition” in business Networks—to cooperate and compete simultaneously, Industrial marketing management 29(5) (2000) 411-426. [41] R.M. Axelord, The Ezoition of Cooperion, Basic Books, 1984. [42] D.R. Gnyawali, R. Madhavan, Cooperative networks and competitive dynamics: A structural embeddedness perspective, Academy of Management review 26(3) (2001) 431-445. [43] E.M. Porter, Techniques for Analyzing Industries and Competitors, New York: Free Press, 1980. [44] M.E. Porter, V.E. Millar, How information gives you competitive advantage, Harvard Business Review Reprint Service, 1985. [45] J. Barney, Firm resources and sustained competitive advantage, Journal of management 17(1) (1991) 99-120. [46] J. Bardeen, W.H. Brattain, The transistor, a semi-conductor triode, Physical Review 74(2) (1948) 230. [47] M. O'Flaherty, C. Cahill, K. Rodgers, O. Slattery, Validation of numerical models of ceramic pin grid array packages, Microelectronics journal 28(3) (1997) 229-238. [48] H. Ueng, C. Liu, The aluminum bond-pad corrosion in small outline packaged devices, Materials Chemistry & Physics 48(1) (1997) 27-35. [49] W. Brodsky, F. Parker, J. Stafford, Reliability and application of leaded plastic chip carriers, Electronic Packaging and Production (1981) 109-122. [50] L. Zhang, S.-b. Xue, L.-l. Gao, Z. Sheng, S.-l. Yu, Y. Chen, W. Dai, F. Ji, Z. Guang, Reliability study of Sn–Ag–Cu–Ce soldered joints in quad flat packages, Microelectronics Reliability 50(12) (2010) 2071-2077. [51] W. Chenniki, I. Bord-Majek, M. Louarn, V. Gaud, J.-L. Diot, K. Wongtimnoi, Y. Ousten, Liquid crystal polymer for QFN packaging: predicted thermo-mechanical fatigue and design for reliability, Microelectronics Reliability 55(12) (2015) 2793-2798. [52] F.C. Ng, A. Abas, Z. Gan, M.Z. Abdullah, F.C. Ani, M.Y.T. Ali, Discrete phase method study of ball grid array underfill process using nano-silica filler-reinforced composite-encapsulant with varying filler loadings, Microelectronics Reliability 72 (2017) 45-64. [53] L.F. Miller, Controlled collapse reflow chip joining, IBM Journal of Research and Development 13(3) (1969) 239-250. [54] M.J. Wolf, G. Engelmann, L. Dietrich, H. Reichl, Flip chip bumping technology—Status and update, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 565(1) (2006) 290-295. [55] S. Cheng, C.-M. Huang, M. Pecht, A review of lead-free solders for electronics applications, Microelectronics Reliability 75 (2017) 77-95. [56] R. Kisiel, K. Bukat, Z. Drozd, M. Szwech, P. Syryczyk, A. Girulska, Implementation of RoHS technology in electronic industry, Recent Advances in Mechatronics, Springer2007, pp. 313-317. [57] R. Rongen, R. Roucou, P. vd Wel, F. Voogt, F. Swartjes, K. Weide-Zaage, Reliability of Wafer Level Chip Scale Packages, Microelectronics Reliability 54(9-10) (2014) 1988-1994. [58] X. Fan, Wafer level packaging (WLP): fan-in, fan-out and three-dimensional integration, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), IEEE, 2010, pp. 1-7. [59] K. Santosh, Advanced packaging: at the heart of innovation, Advanced Packaging & System Integration Technology Symposium, Yole Développement, 2018, pp. 1-5. [60] K. Tu, Y. Liu, Recent advances on kinetic analysis of solder joint reactions in 3D IC packaging technology, Materials Science and Engineering: R: Reports 136 (2019) 1-12. [61] T.-T. Chou, R.-W. Song, H. Chen, J.-G. Duh, Low thermal budget bonding for 3D-package by collapse-free hybrid solder, Materials Chemistry and Physics (2019) 121887. [62] M. Song, Z. Wei, B. Wang, L. Chen, L. Chen, J.A. Szpunar, Study on copper protrusion of through-silicon via in a 3-D integrated circuit, Materials Science and Engineering: A 755 (2019) 66-74. [63] L. Zhang, Z.-q. Liu, S.-W. Chen, Y.-d. Wang, W.-M. Long, Y.-h. Guo, S.-q. Wang, G. Ye, W.-y. Liu, Materials, processing and reliability of low temperature bonding in 3D chip stacking, Journal of Alloys and Compounds 750 (2018) 980-995. [64] G. Poupon, N. Sillon, D. Henry, C. Gillot, A. Mathewson, L. Di Cioccio, B. Charlet, P. Leduc, M. Vinet, P. Batude, System on wafer: a new silicon concept in SiP, Proceedings of the IEEE 97(1) (2009) 60-69. [65] J.H. Lau, Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration, 2011 international symposium on advanced packaging materials (APM), IEEE, 2011, pp. 462-488. [66] C. Yu, The 3rd dimension-more life for Moore's Law, 2006 International Microsystems, Package, Assembly Conference Taiwan, IEEE, 2006, pp. 1-6. [67] M. Wolf, P. Ramm, A. Klumpp, H. Reichl, Technologies for 3D wafer level heterogeneous integration, 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, IEEE, 2008, pp. 123-126. [68] M. Harzi, H. Abusenenh, S. Krichen, Solving The Yield Optimization Problem for Wafer to Wafer 3d Integration Process, Procedia-Social and Behavioral Sciences 195 (2015) 1905-1914. [69] G. Roelkens, J. Van Campenhout, J. Brouckaert, D. Van Thourhout, R. Baets, P.R. Romeo, P. Regreny, A. Kazmierczak, C. Seassal, X. Letartre, III-V/Si photonics by die-to-wafer bonding, Materials Today 10(7-8) (2007) 36-43. [70] Y. Tang, S. Luo, G. Li, Z. Yang, R. Chen, Y. Han, C. Hou, Optimization of the thermal reliability of a four-tier die-stacked SiP structure using finite element analysis and the Taguchi method, Microelectronics Journal 73 (2018) 18-23. [71] Y.-K. Ko, H.T. Fujii, Y.S. Sato, C.-W. Lee, S. Yoo, High-speed TSV filling with molten solder, Microelectronic engineering 89 (2012) 62-64. [72] G. Fu, Y. Su, W. Guo, B. Wan, Z. Zhang, Y. Wang, Life prediction methodology of system-in-package based on physics of failure, Microelectronics Reliability 88 (2018) 173-178. [73] P. Ramm, A. Klumpp, R. Merkel, J. Weber, R. Wieland, A. Ostmann, J. Wolf, 3D system integration technologies, MRS Online Proceedings Library Archive 766 (2003). [74] M. Motoyoshi, Through-silicon via (TSV), Proceedings of the IEEE 97(1) (2009) 43-48. [75] C.-T. Ko, K.-N. Chen, Wafer-level bonding/stacking technology for 3D integration, Microelectronics reliability 50(4) (2010) 481-488. [76] P. De Moor, W. Ruythooren, P. Soussan, B. Swinnen, K. Baert, C. Van Hoof, E. Beyne, Recent advances in 3D integration at IMEC, MRS Online Proceedings Library Archive 970 (2006). [77] R. Beica, T. Buisson, A. Pizzagalli, 3D packaging technologies and applications, latest challenges and supply chain activities, ECS Transactions 61(6) (2014) 11-16. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72458 | - |
| dc.description.abstract | 隨著電子產業的發展，人工智能、物聯網及高效能運算等新應用，都需要半導體產業的支持應用。為達到更小的體積，節能、高效及低成本等的異質整合型晶片，當前摩爾定律（Moore's Law）已遇到瓶頸，因此，利用半導體3D堆疊封裝技術，將成為延續摩爾定律的重要關鍵。
本論文主要在說明半導體先進3D封裝技術的產業發展現況，藉由3D封裝技術及產業結構分析，對未來3D封裝市場情況提供建議。在3D封裝的技術創新初探研究中，利用先進封裝廠利用現有製程設備，研究探討可行的3D堆疊封裝結構。晶圓代工廠因應客戶的高階製程需求，開始發展封裝產業，使得晶圓代工產業與封裝產業將形成新的競合關係。 最後，藉由不同3D封裝產業面向進行分析探討找出合適的策略建議，進而推展成為最具有潛力的封裝方法，有助於未來台灣半導體3D封裝技術的發展。 | zh_TW |
| dc.description.abstract | With the development of the electronics industry, new applications such as artificial intelligence, Internet of Things, and high-performance computing require the support of the semiconductor industry. Moore's Law has encountered bottlenecks in order to achieve smaller, energy-efficient, efficient and low-cost heterogeneous integrated wafers. Therefore, the use of semiconductor 3D stacked packaging technology will become an important key to the continued Moore's Law.
This thesis is mainly to explain the current development of semiconductor advanced 3D packaging technology industry, through 3D packaging technology and industry analysis, to provide advice on the future 3D packaging market. In the preliminary study of 3D packaging technology innovation, the advanced packaging factory utilizes existing process equipment to study and explore the feasible 3D stacked package structure. The wafer foundries begin to develop the packaging industry in response to customers' high-level process requirements, which will enable the foundry industry and the packaging industry to form a new co-opetition relationship. Finally, through the analysis and discussion of different 3D packaging industries, this study is to find the appropriate strategic advice, and then promoted to become the most promising packaging method, and to help the future development of Taiwan's semiconductor 3D packaging technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:59:26Z (GMT). No. of bitstreams: 1 ntu-108-P06546002-1.pdf: 1884745 bytes, checksum: 9ed998dcb465c594f809588d7724f218 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 目錄
口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii 目錄 iv 圖目錄 vi 第一章 緒論 1 1.1研究背景與動機 1 1.2 3D封裝技術探討 3 1.3研究目的 11 第二章 產業分析方法 13 2.1技術創新模式 13 2.2產業競合關係 15 2.3產業競爭分析 16 第三章 半導體封裝的技術發展 18 3.1傳統封裝的技術發展 18 3.2晶圓級封裝的技術發展 22 3.3 3D封裝技術的定義與特性 23 第四章3D封裝的技術與發展現況 26 4.1 3D封裝技術的產業現況 26 4.2 3D封裝技術的發展特點 28 4.3 3D封裝技術的瓶頸與挑戰 33 第五章 封裝技術的競爭分析 35 5.1 3D封裝技術的初探研究 35 5.2 3D封裝技術的競合關係分析 42 5.3 3D封裝技術的SWOT分析 44 第六章 結論與建議 48 參考文獻 51 | |
| dc.language.iso | zh-TW | |
| dc.subject | 摩爾定律 | zh_TW |
| dc.subject | 異質整合 | zh_TW |
| dc.subject | 技術創新 | zh_TW |
| dc.subject | 3D封裝 | zh_TW |
| dc.subject | 競合關係 | zh_TW |
| dc.subject | 3D Packaging | en |
| dc.subject | Heterogeneous Integration | en |
| dc.subject | Technology Innovation | en |
| dc.subject | Co-opetition Relationship | en |
| dc.title | 半導體先進3D封裝技術及產業分析研究 | zh_TW |
| dc.title | Semiconductor Advanced 3D Packaging Technology and
Industry Analysis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊曙榮,陳文智 | |
| dc.subject.keyword | 3D封裝,摩爾定律,異質整合,技術創新,競合關係, | zh_TW |
| dc.subject.keyword | 3D Packaging,Heterogeneous Integration,Technology Innovation,Co-opetition Relationship, | en |
| dc.relation.page | 55 | |
| dc.identifier.doi | 10.6342/NTU201902380 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-08-05 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 工業工程學研究所 | zh_TW |
| 顯示於系所單位： | 工業工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-108-1.pdf 未授權公開取用 | 1.84 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。