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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李坤彥(Kung-Yen Lee) | |
| dc.contributor.author | Yi-Che Su | en |
| dc.contributor.author | 蘇奕哲 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:26:34Z | - |
| dc.date.available | 2023-08-20 | |
| dc.date.copyright | 2018-08-20 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-17 | |
| dc.identifier.citation | 參考文獻
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Qiu et al., “Study of defect states in GaN films by photoconductivity measurement,” Applied Physics Letters, vol. 66, no. 20, pp. 2712-2714, 1995/05/15, 1995. [9] B. J. Baliga, Fundamentals of Power Semiconductor Devices: Springer, 2010. [10] M. S. Adler et al., “The evolution of power device technology,” IEEE Transactions on Electron Devices, vol. 31, no. 11, pp. 1570-1591, 1984. [11] J. W. Palmour et al., 6H-silicon carbide power devices for aerospace applications, 1993. [12] L. Chang et al., “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000, pp. 719-722. [13] I. Polishchuk, and C. Hu, “Polycrystalline silicon/metal stacked gate for threshold voltage control in metal–oxide–semiconductor field-effect transistors,” Applied Physics Letters, vol. 76, no. 14, pp. 1938-1940, 2000/04/03, 2000. [14] S. C. Sun, and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,” IEEE Transactions on Electron Devices, vol. 27, no. 2, pp. 356-367, 1980. [15] J. H. Hohl, and K. F. Galloway, “Analytical Model for Single Event Burnout of Power MOSFETs,” IEEE Transactions on Nuclear Science, vol. 34, no. 6, pp. 1275-1280, 1987. [16] D. A. Neamen, Semiconductor physics and devices, 2003. [17] R. E. Stahlbush et al., “Basal plane dislocation reduction in 4H-SiC epitaxy by growth interruptions,” Applied Physics Letters, vol. 94, no. 4, pp. 041916, 2009/01/26, 2009. [18] P. G. Neudeck, W. Huang, and M. Dudley, “Breakdown degradation associated with elementary screw dislocations in 4H-SiC p+n junction rectifiers,” Solid-State Electronics, vol. 42, no. 12, pp. 2157-2164, 1998/12/01/, 1998. [19] I. Abdullah et al., “Surface defect on SiC ohmic contact during thermal annealing,” in 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012, pp. 740-743. [20] L. D. Stevanovic et al., “Recent advances in silicon carbide MOSFET power devices,” in 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 401-407. [21] S. Salemi et al., “The effect of different passivations on near interface trap density of 4H-SiC/SiO2 structures,” in 2011 International Semiconductor Device Research Symposium (ISDRS), 2011, pp. 1-2. [22] J. A. Cooper, Jr. et al., “Status and prospects for SiC power MOSFETs,” Electron Devices, IEEE Transactions on, vol. 49, no. 4, pp. 658-664, 2002. [23] S. Potbhare et al., 'Characterization of 4H-SiC MOSFET Interface Trap Charge Density Using a First Principles Coulomb Scattering Mobility Model and Device Simulation.',in 2005 International Conference On Simulation of Semiconductor Processes and Devices, pp. 95-98. [24] S. C. Witczak et al., The determination of Si-SiO2 interface trap density in irradiated four-terminal VDMOSFETs using charge pumping, 1997. [25] D. Okamoto et al., “Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide,” IEEE Electron Device Letters, vol. 31, no. 7, pp. 710-712, 2010. [26] D. Okamoto et al., “Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation,” IEEE Electron Device Letters, vol. 35, no. 12, pp. 1176-1178, 2014. [27] H. Yano et al., High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face, 2000. [28] O. Teruyuki et al., “Investigation of nitridation and oxidation reactions at SiC/SiO 2 interfaces in NO annealing and modeling of their quantitative impacts on mobility of SiC MOSFETs,” Japanese Journal of Applied Physics, vol. 56, no. 10, pp. 106502, 2017. [29] R. Kies et al., 'Temperature Dependence of Fowler-Nordheim Emission Tunneling Current in MOS Structures.', in 24th European Solid State Device Research Conference ,pp. 507-510. [30] C. Lifeng, Y. Ma, and T. Lilin, 'Modeling on direct tunneling current in ultra-thin oxide NMOSFET considering quantum mechanics.',in 23rd International Conference on Microelectronics Proceedings (Cat. No.02TH8595),pp. 483-486 vol.2. [31] A. W. Ludikhuize, “A review of RESURF technology,” in 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), 2000, pp. 11-18. [32] S. Yamauchi et al., “200V Super Junction MOSFET Fabricated by High Aspect Ratio Trench Filling,” in 2006 IEEE International Symposium on Power Semiconductor Devices and IC's, 2006, pp. 1-4. [33] J. Sakakibara et al., 600V-class Super Junction MOSFET with High Aspect Ratio P/N Columns Structure, 2008. [34] P. Kondekar, H. S. Oh, and Y. B. Kim, “Study of the degradation of the breakdown voltage of a super-junction power MOSFET due to charge imbalance,” Journal of the Korean Physical Society vol. 48, pp. 624-630, 2006. [35] B. Liang et al., “Simulation and analysis of the breakdown mechanism and characteristics of super junction structure,” in 2011 International Conference on Electronics, Communications and Control (ICECC), 2011, pp. 467-470. [36] W. Saito, “Theoretical limits of superjunction considering with charge imbalance margin,” in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015, pp. 125-128. [37] Y. Onishi et al., “24 mΩcm2 680 V silicon superjunction MOSFET,” in Power Semiconductor Devices and ICs, 2002, pp. 241-244. [38] C.-L. Wang, and J. Sun, “An oxide filled extended trench gate super junction MOSFET structure,” Chinese Physics B, vol. 18, no. 3, pp. 1231, 2009. [39] E. G. Kang, “Design and Fabrication of Super Junction MOSFET for Industrial Applications,” Electrical and Electronic Engineering, vol. 6, pp. 6-10, 2016. [40] T. Hatakeyama et al., “Physical Modeling and Scaling Properties of 4H-SiC Power Devices,” in 2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005, pp. 171-174. [41] A. G. Chynoweth, “Ionization Rates for Electrons and Holes in Silicon,” Physical Review, vol. 109, no. 5, pp. 1537-1540, 03/01/, 1958. [42] infineon. https://www.infineon.com/dgdl/Infineon-FF11MR12W1M1_B11-DS-v02_00-EN.pdf?fileId=5546d4625bd71aa0015c0c327a620aea. [43] A. Ortiz-Conde et al., “A review of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 42, no. 4, pp. 583-596, 2002/04/01/, 2002. [44] O. D. Kristensen, Modeling of Failure Mechanisms in SiC MOSFETs Subject to Short-Circuits, 2017. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72163 | - |
| dc.description.abstract | 近年來，市場對功率半導體元件追求高效率與小尺寸，且為了符合節能與降低系統功率損耗的需求趨勢，各廠商均不斷開發新型的高能源轉換效率的元件，以滿足高效率、可靠度、小型化等要求。功率電晶體在電源供應裝置中是最為受到關注的元件，由於碳化矽材料的材料特性，使得碳化矽金氧半場效電晶體(MOSFET)比傳統矽功率MOSFET有更好的效能與熱表現。
本論文利用TCAD Sentaurus進行4H-SiC碳化矽金氧半場效電晶體的設計，並針對元件結構進行電性的分析，論文一開始對一般的碳化矽MOSFET做閘極氧化層厚度、JFET寬度及混合磊晶層在順向時的表現進行優化，並帶入近年來蓬勃發展的超級接面結構，利用其電荷補償的特性增加逆向時的崩潰電壓，並以英飛凌的CoolSiC^TM產品為目標，模擬的結果成功達到崩潰電壓1200伏特以上，特徵導通電阻小於5 mΩ∙cm^2 且臨界電壓3至5伏特的規格。 | zh_TW |
| dc.description.abstract | In recent years, the market has pursued high efficiency and small size for power semiconductor devices to achieve the demand of energy saving and system power loss reduction. Manufacturers have continuously developed new higher energy conversion efficiency devices to attain high efficiency and reliability. Power transistors are the most attractive attention, due to the material properties of silicon carbide, SiC MOSFET has better efficiency and thermal performance than traditional silicon power MOSFET.
In this paper, TCAD Sentaurus is used to design 4H-SiC metal oxide semiconductor field effect transistor and then simulate its electric performance. We analyze the simulation results and optimize the device’s performance by discussing the gate oxide thickness, JFET width and mixed epitaxial layer to optimize the forward electrical performance. We use the charge compensation characteristics of the super junction to increase the breakdown voltage and aim at Infineon's CoolSiC^TM product, the simulation results successfully reach the breakdown voltage of 1200 volts or more, the specific on-resistance is less than 5 mΩ∙cm^2 and threshold voltage is 3 to 5 volts. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:26:34Z (GMT). No. of bitstreams: 1 ntu-107-R05525106-1.pdf: 3422363 bytes, checksum: 085230d0ad142bd5eb2925d96eff3c15 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 中文摘要 i
Abstract ii 目錄 iii 圖目錄 v 表目錄 viii 第一章 緒論 1 1.1前言 1 1.2 碳化矽材料的性質 2 1.3 研究動機 5 第二章 元件結構原理 6 2.1 常見的功率電晶體種類簡介 6 2.2功率元件介紹與結構 7 2.2.1 垂直式雙擴散金氧半場效電晶體的順向導通機制 10 2.2.2垂直式雙擴散金氧半場效電晶體的逆向崩潰機制 14 2.3碳化矽功率MOSFET 發展中的困難 17 2.3.1 Power MOSFET 元件特性的發展理論極限 17 2.3.2 低載子通道遷移率 18 2.3.3 氧化層穩定度 19 2.4超級接面的發展 22 2.4.1超級接面的原理與結構 22 2.4.2 超級接面的製程方法 25 2.4.3超級接面應用於碳化矽金氧半場效電晶體 27 第三章 模擬環境 29 3.1 模擬環境 29 3.2 模擬方法 30 第四章 模擬結果分析與討論 34 4.1元件初步設計 34 4.2 JFET的寬度對元件電性之影響 44 4.3 使用不同磊晶濃度對元件電性的影響 47 4.4 閘極氧化層的厚度對元件電性之影響 51 4.5 浮動式P型結構對元件電性之影響 54 4.5.1 一根P型的浮動式結構(版本一) 54 4.5.2 增加版本一之P結構的摻雜濃度25%(版本二) 58 4.5.3 於第七層的磊晶層多加一根P型浮動式結構(版本三) 61 4.5.4 於第二層的磊晶層多加一根P型浮動式結構(版本四) 65 4.5.5 改變P型結構的位置(版本五) 69 4.5.6 混合磊晶層(版本六) 72 4.6 整理與討論 74 第五章 結論與未來展望 76 參考文獻 77 | |
| dc.language.iso | zh-TW | |
| dc.subject | 崩潰電壓 | zh_TW |
| dc.subject | 4H-SiC | zh_TW |
| dc.subject | 碳化矽 | zh_TW |
| dc.subject | 金氧半場效電晶體(MOSFET) | zh_TW |
| dc.subject | CoolSiC^TM | zh_TW |
| dc.subject | TCAD | zh_TW |
| dc.subject | CoolSiC^TM | en |
| dc.subject | MOSFET | en |
| dc.subject | TCAD | en |
| dc.subject | Breakdown Voltage | en |
| dc.subject | 4H-SiC | en |
| dc.title | 新穎碳化矽金氧半場效電晶體結構設計與模擬 | zh_TW |
| dc.title | The Design and Simulation of Novel SiC Metal Oxide Semiconductor Field Effect Transistor Structure | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李佳翰,黃智方 | |
| dc.subject.keyword | 4H-SiC,碳化矽,金氧半場效電晶體(MOSFET),CoolSiC^TM,TCAD,崩潰電壓, | zh_TW |
| dc.subject.keyword | 4H-SiC,MOSFET,CoolSiC^TM,TCAD,Breakdown Voltage, | en |
| dc.relation.page | 80 | |
| dc.identifier.doi | 10.6342/NTU201803864 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-17 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 工程科學及海洋工程學研究所 | zh_TW |
| 顯示於系所單位： | 工程科學及海洋工程學系 | |
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