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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71830完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林坤佑 | |
| dc.contributor.author | Chun-Ming Lin | en |
| dc.contributor.author | 林俊名 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:11:19Z | - |
| dc.date.available | 2021-11-08 | |
| dc.date.copyright | 2018-11-08 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-10-30 | |
| dc.identifier.citation | [1] Z. El Alaoui Ismaili et al., “Very wide range frequency synthesizer architecture for avionic SDR applications,” in Proc. of IEEE ICUWB, Oct. 2015, pp. 796–799.
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Natarajan, 'A 74.6GHz–83.6GHz digitally controlled oscillator with 370kHz frequency resolution in 65nm CMOS,' 2016 IEEE Radio and Wireless Symposium (RWS), Austin, TX, 2016, pp. 176-178. [29] Z. Li and K. K. O, 'A 1-V low phase noise multi-band CMOS voltage controlled oscillator with switched inductors and capacitors,' 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, Forth Worth, TX, 2004, pp. 467-470. [30] Liu Qing, Sun Jiangtao, S. Kurachi, N. Itoh and T. Yoshimasu, 'A switched-inductor based VCO with an ultra-wideband tuning range of 87.6 %,' 2009 IEEE 8th International Conference on ASIC, Changsha, Hunan, 2009, pp. 355-358. [31] Z. Safarian and H. Hashemi, 'Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1830-1843, Aug. 2009. [32] Kissinger, Dietmar (2012). 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Liang-Hung, 'Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture,' IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1942-1952, Sept. 2007. [45] L. Jri, et al., 'A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology,' IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008. [46] L. Lianming, et al., 'Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank,' IEEEJournal of Solid-State Circuits, vol. 44, no. 7, pp. 1950-1958, Jul. 2009. [47] S.-W. Tam, H.-T. Yu, Y. Kim, E. Socher, M. C. F. Chang, and T. Itoh,“A dual band mm-wave CMOS oscillator with left-handed resonator,” RFIC Tech. Dig., Jun. 2009, pp. 477–480. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71830 | - |
| dc.description.abstract | 隨著時代的推近，積體電路的技術獲得了大幅的進步，無線通訊晶片的發展趨勢也朝著高度積體化、低成本、可支援多種通信標準的方向邁進。在一個射頻收發機裡必須要有一個可以產生高頻譜純度信號的頻率合成器，以避免調變後的信號干擾到鄰近通道以及信號雜訊比的降低。在頻率合成器裡，振盪器是一個非常關鍵的電路，其可調頻率範圍、相位雜訊表現、功率消耗對整體頻率合成器的特性有非常顯著的影響。
本篇論文針對兩種不同的應用設計了兩種振盪器結構。第一個電路以軟體定義無線電的應用為設計目標，在90 nm CMOS製程上實現了一個寬頻、低相位雜訊、高頻率解析度的數位控制振盪器。在開關式電容的架構上搭配提高頻率解析度和雜訊過濾的電路技術，達成了在1伏特的供電電壓下，可調頻率範圍8.14-11.9 GHz，直流電流9.4-24.5毫安培，頻率解析度230 Hz，並且量測到的相位雜訊介於-108.4和-115.4 dBc/Hz之間。此外，我們提出一個可以對寬頻低相位雜訊振盪器進行最佳化的設計技巧和方法，稱為Ceq-Ctune diagram。 第二個電路以未來自動化駕駛技術中所使用的汽車雷達系統為設計目標，在90nm CMOS製程上實現了一個具有靜電放電保護設計的24 GHz和77 GHz雙頻段數位控制駐波振盪器。在改良的駐波振盪器架構上採用DiCAD傳輸線作為頻率調整機制，達成了在1.2伏特的供電電壓下，可調頻率範圍20.6-22.4 GHz和76.1-77.1 GHz，直流電流6和14毫安培，並且量測到的相位雜訊介於-94.4和-103.2 dBc/Hz之間。 | zh_TW |
| dc.description.abstract | As time progresses, the technology of integrated circuit gains a significant development. The trend of wireless communication chips is heading to high-level integration, low cost and capability of supporting multiple communication standards. In radio-frequency transceivers and receivers, it is necessary to have a frequency synthesizer that can generate high purity signals. High purity signal for carrier ensures the modulated signal against the out-band-emission and the reduction of signal-to-noise ratio. In a frequency synthesizer, the oscillator is a crucial building block, and its frequency tuning range, phase noise, power consumption have significant impacts on the overall performance of the system.
In this thesis, two oscillators for two different applications are designed. In the first circuit, an integrated wide tuning range, low phase noise and high frequency resolution digitally controlled oscillator (DCO) in 90 nm CMOS technology for software-defined radio (SDR) frequency synthesizers is presented. The switched capacitor equipped with fine frequency resolution and tail noise filtering techniques are adopted to achieve a wide frequency range from 8.14–11.90 GHz with power consumption varying from 9.4–24.5 mA under 1-V supply. The measured phase noise is −108.4 to −115.4 dBc/Hz at 1-MHz offset. The frequency tuning is controlled by 6-bit coarse-tuning, 6-bit mid-tuning, and 16-bit fine-tuning. The measured average frequency resolution is 230 Hz. Furthermore, a design technique what we term as Ceq-Ctune diagram and the methodology for designing wide tuning range and low phase noise oscillator in single core are also presented. In the second circuit, an integrated 24 GHz and 77 GHz dual-band digitally-controlled standing wave oscillator with ESD protection design for the automotive radar system used in autonomous driving technology is presented. The modified standing wave oscillator topology equipped with digitally-controlled artificial dielectric (DiCAD) transmission line is adopted to achieve a dual band operation in 20.6–22.4 GHz and 76.1–77.1 GHz with power consumption of 6 mA and 14 mA under 1.2-V supply. The measured phase noise is −94.4 to −103.2 dBc/Hz at 1-MHz offset. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:11:19Z (GMT). No. of bitstreams: 1 ntu-107-R04942019-1.pdf: 14137149 bytes, checksum: 33f295cc62d2454c7192f7af637e954a (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xvii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contributions 1 1.3 Thesis Organization 2 Chapter 2 A Wideband, Low Noise, and High Resolution Digitally Controlled Oscillator for SDR Applications 3 2.1 Introduction 3 2.2 Proposed DCO topology 6 2.2.1 Coarse-tuning bank 7 2.2.2 Mid-tuning bank 14 2.2.3 Fine-tuning bank 15 2.2.4 Digitally-controlled current source 18 2.2.5 Noise filtering technique 19 2.2.6 Output buffers 22 2.2.7 Serial-in-parallel-out shift register 23 2.3 Design flow and methodology 25 2.4 Layout 33 2.4.1 Resonance inductor 33 2.4.2 Noise filtering inductor 35 2.4.3 Coarse-tuning bank 37 2.4.4 Mid-tuning bank 38 2.4.5 Fine-tuning bank 38 2.4.6 Digitally-controlled current source 39 2.4.7 SIPO shift register 41 2.4.8 Overall Layout 42 2.5 Simulation 43 2.5.1 Coarse-tuning 43 2.5.2 Mid-tuning 45 2.5.3 Fine-tuning 47 2.5.4 SIPO shift register 48 2.6 Measurement 50 2.6.1 Environment setup 50 2.6.2 Measurement results 56 2.7 Debugging and troubleshooting 64 2.8 Summary 70 Chapter 3 A 24 GHz and 77 GHz Dual-Band Digitally-Controlled Standing Wave Oscillator with ESD Protection Design 71 3.1 Introduction 71 3.2 Architecture of dual-band millimeter wave clock generation 74 3.3 Multiple-mode oscillation of standing wave oscillator 76 3.4 Proposed SWO topology 79 3.4.1 Transmission line architecture 80 3.4.2 Cross-coupled pairs 86 3.4.3 Frequency tuning mechanism-DiCAD 88 3.4.4 Output buffers 92 3.5 Design flow and methodology 93 3.6 Layout 94 3.6.1 DiCAD transmission line and switch 94 3.6.2 Digitally-controlled current source 95 3.6.3 SIPO shift register 96 3.6.4 Overall layout 96 3.7 Simulation 97 3.7.1 Low band oscillation 97 3.7.2 High band oscillation 99 3.8 Measurement 101 3.8.1 Bond wire and PCB layout 101 3.8.2 Measurement environment 102 3.8.3 Measurement results 103 3.9 Debugging and troubleshooting 108 3.9.1 On-chip ESD design 108 3.9.2 Off-chip ESD design 118 3.9.3 Measurement results of modified design 123 3.10 Summary 139 Chapter 4 Conclusion 140 REFERENCE 141 | |
| dc.language.iso | en | |
| dc.subject | 靜電放電保護 | zh_TW |
| dc.subject | 駐波振盪器 | zh_TW |
| dc.subject | 雙頻段 | zh_TW |
| dc.subject | Ceq-Ctune diagram | zh_TW |
| dc.subject | 雜訊過濾 | zh_TW |
| dc.subject | 頻率解析度 | zh_TW |
| dc.subject | 相位雜訊 | zh_TW |
| dc.subject | 數位控制振盪器 | zh_TW |
| dc.subject | Standing-wave oscillator (SWO) | en |
| dc.subject | phase noise | en |
| dc.subject | frequency resolution | en |
| dc.subject | Noise filtering | en |
| dc.subject | Ceq-Ctune diagram | en |
| dc.subject | dual-band | en |
| dc.subject | Digitally-controlled oscillator (DCO) | en |
| dc.subject | Digitally-controlled artificial dielectric(DiCAD) | en |
| dc.subject | Electrostatic discharge (ESD) protection | en |
| dc.title | 寬頻低相位雜訊數位控制振盪器與車用雙頻段駐波振盪器之設計與最佳化 | zh_TW |
| dc.title | Design and Optimization of Wide Tuning Range, Low Phase Noise Digitally-Controlled Oscillator and Automotive Dual-Band Standing-Wave Oscillator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張鴻埜,高?堯,蔡政翰,蔡作敏 | |
| dc.subject.keyword | 數位控制振盪器,相位雜訊,頻率解析度,雜訊過濾,Ceq-Ctune diagram,雙頻段,駐波振盪器,靜電放電保護, | zh_TW |
| dc.subject.keyword | Digitally-controlled oscillator (DCO),phase noise,frequency resolution,Noise filtering,Ceq-Ctune diagram,dual-band,Standing-wave oscillator (SWO),Digitally-controlled artificial dielectric(DiCAD),Electrostatic discharge (ESD) protection, | en |
| dc.relation.page | 148 | |
| dc.identifier.doi | 10.6342/NTU201804250 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-10-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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