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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Tzu-Heng Wang | en |
dc.contributor.author | 王子珩 | zh_TW |
dc.date.accessioned | 2021-06-17T06:04:40Z | - |
dc.date.available | 2025-11-03 | |
dc.date.copyright | 2020-11-12 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-11-03 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71616 | - |
dc.description.abstract | 隨著AI與IoT日漸普及,存儲裝置的需求也與日俱增,然目前傳統存儲裝置並無法應付這樣的的需求,例如快閃記憶體苦於耐用度不足,而快取記憶體雖有足夠的存取速度但容量太小等。因此,新型態記憶體的需求因應而生,目前最受矚目的一群稱為SCM (Storage Class Memory, 儲存級記憶體),其特色是不俗的存取速度與較以往快取記憶體更大的容量,而電阻式記憶體(RRAM)便是其中一員。和傳統記憶體相比,RRAM的優點有記憶密度大(NOR FLASH的2-4倍)、高操作速度(~140MB/秒)與更好的耐用度(>106次)等。 RRAM一般常用的材料主要為TMO (Transitional Metal Oxides, 過度金屬氧化物),並以此組成MIM(金屬-半導體-金屬)的三明治結構,並確立了RRAM的特性指標,以此為根基,學者們開始找尋替換新材料的可能性。隨著近年材料科學的蓬勃發展,二維材料一躍而上映入人們的眼簾,也開始有研究團隊應用二維材料來製作RRAM,例如h-BN, MoS2和MoTe2等。二維材料的主要製備可以透過CVD沉積與機械剝離法,而在本篇論文中則以機械剝離法為製作方法,並佐以其他製程來測試製作元件在不同環境下的表現。 首先,我們將以二硫化鉬作為主動層材料,而後透過常溫量測得到的數據找出面積對於元件開關比的關聯性,更進一步以變溫量測探討電阻值的改變,以及判斷其電流傳導特性等。其後我們亦將材料替換為六方氮化硼並發現其導電特性由於屬於較高能階材料之緣故,與二硫化鉬有所不同。 而後我們發現機械剝離法材料有較嚴重的高阻態漏流問題,並透過文獻回顧發現是由於缺乏晶格邊界缺陷導致,為了優化機械剝離法RRAM的電特性,我們希望通過製程方法在材料中製造缺陷,並解決切換時機械剝離法元件的漏流問題,以此將兩種方法的優點結合起來。在本文中,我們將透過使用RIE使得MoS2表面氧化並充斥缺陷的方法。如此一來,我們可以模擬CVD元件的晶格邊界並提高元件的開關比。 在製作單顆RRAM成功並確立其標準電性後,我們便試著將其與二維材料電晶體串接,形成一個獨立的量測單元,並觀察其在電晶體作為限流器的情形下兩者的匹配程度與RRAM是否仍能正常運作,並在後續透過其他製程手段例如氧化電漿製程與材料堆疊等成功解決兩者匹配性的問題。 | zh_TW |
dc.description.abstract | Since AI and IoT become more and more popular, the demand of storage devices is skyrocketing. However, conventional storage devices cannot meet the requirements. For example, FLASH possess large capacity but low device endurance, and SRAM has quick data transport speed but low capacity. Therefore, a new type of memory emerges as the times require which is so-called SCM (Storage Class Memory). It is famous for its better data transport speed than FLASH and the storage capacity which is bigger than cache does, and RRAM is a member in the SCM family. Comparing with conventional memory, RRAM possess some specific characteristics: higher memory density (2-4x larger than NOR FLASH), high operation speed (~140MB/s), and better endurance (~106 times switching). RRAM is composed with TMOs (Transitional Metal Oxides) and two metal electrodes to form a MIM structure, and TMOs are used as the active layer. After that, the characteristic indexes of RRAM are established. On that basis, researchers start to find the probability of substituting the active layer material. As the development of material science, 2D materials become more and more eye-catching. Recently, there are some research groups that apply 2D materials such as h-BN, MoS2, MoTe2 to the active layer. There are mainly two methods to obtain 2D materials, mechanical exfoliation and CVD (Chemical Vapor Deposition). In this thesis, the mechanical exfoliation method is mainly adopted, and the performance of devices made under different process conditions have been investigated. First, we use molybdenum disulfide as the active layer material, and then find out the correlation between the electrode overlapped area and the switching ratio of the device through the data obtained from the measurement under room temperature, then further measure the change of resistance value at various temperature to determine its current conduction characteristics. Later, we also replace the active layer material with hexagonal boron nitride and find out that its electrical conductivity is different from that of molybdenum disulfide due to its higher band gap. Then we find that the mechanical exfoliated RRAM suffers a serious HRS leakage problem, and through paper survey we found that it is caused by the lack of grain boundary defects. To optimize electrical characteristic of mechanical exfoliated RRAM, we would like to create defects in material via process method and solve the damage problem of mechanical exfoliated device when switching, so we can combine advantages of CVD and exfoliation methods. In this thesis, we will demonstrate a method that uses RIE to induce oxygen ions and vacancy in surface of MoS2 and oxidize it. This way, we can simulate the grain boundaries like those of CVD devices and enhance the switching ratio. After successfully fabricating a single RRAM and establishing its statical standard electrical properties, we tried to connect it in series with a two-dimensional material transistor to form an independent measurement unit, in which the transistor acts as a current limiter. The degree of matching between the RRAM and transistor is investigated, and the problem of compatibility can be successfully solved later through other process methods such as plasma oxide process and material stacking. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:04:40Z (GMT). No. of bitstreams: 1 U0001-0311202018233700.pdf: 5391766 bytes, checksum: eb9888a0c8f151af703cd29e4ba9ba00 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 口試委員審定書 i 論文致謝 1 摘要 4 Abstract 6 Table of Contents 8 List of Figures 11 List of Tables 14 第1章. 緒論 15 1.1 研究目的與欲解決之問題 15 1.1.1 存儲裝置發展現況及其未來發展 15 1.1.2 二維材料的興起與發展近況 17 1.2 電阻式記憶體之研究現況 20 1.2.1 電阻式記憶體發展史與評價項目 20 1.2.2 傳統電阻式記憶體之研究現況 20 1.2.3 有機光電材料電阻式記憶體之研究現況 21 1.3 電阻式記憶體之操作原理 23 1.3.1 電橋式記憶體之操作原理 23 1.3.2 空缺式記憶體之操作原理 24 1.3.3 電阻式記憶體圖形判讀 24 1.4 論文導覽 27 第2章. 以二維材料為主動層之電阻式記憶體 28 2.1 二維材料電阻式記憶體之研究現況 28 2.2 以鈦金為電極之空缺式二硫化鉬記憶體 29 2.2.1 二硫化鉬材料之能帶與化學結構 29 2.2.2 二硫化鉬之常見用途-作為電晶體 30 2.2.3 空缺式二硫化鉬記憶體結構之研究現況 32 2.2.4 元件結構與製程 33 2.2.5 元件電性與分析 35 2.3 以六方氮化硼為材料之電阻式記憶體 37 2.3.1 六方氮化硼材料之能帶與化學結構 37 2.3.2 六方氮化硼記憶體結構之研究現況 38 2.3.3 元件結構與製程 38 2.3.4 元件電性與分析 39 2.4 二硫化鉬與六方氮化硼電阻式記憶體之特性比較 41 2.5 本章結論與未來展望 42 第3章. RRAM之導通機制與製程改善 43 3.1 以變溫量測探討電阻式記憶體之電流傳導機制 43 3.1.1 傳統電阻式記憶體機制探討文獻回顧 43 3.1.2 變溫度量測之實驗方法與架設 49 3.1.3 以所得數據分析元件傳導特性與活化能 50 3.2 以氧電漿轟擊製程優化電阻式記憶體 56 3.2.1 二維材料氧化之相關文獻回顧 56 3.2.2 氧化程度測試、元件結構與製程 56 3.2.3 元件電性與分析 59 3.3 本章結論與未來展望 62 第4章. 電阻式記憶體-電晶體串接(1T1R)結構之研究 63 4.1 1T1R結構簡介 63 4.2 以二硫化鉬作為電晶體與記憶體之1T1R結構 64 4.2.1 元件結構與製程 64 4.2.2 元件電性分析 65 4.2.3 遭遇之問題與嘗試解決方向 66 4.3 以氧電漿轟擊改進1T1R結構 68 4.3.1 使用氧電漿轟擊之方法與目的 68 4.3.2 氧電漿製程對於二硫化鉬記憶體之電性改進 68 4.3.3 改進後記憶體與電晶體之匹配情形 68 4.4 以二維材料堆疊改進1T1R結構 70 4.4.1 使用二維材料堆疊之原理方法與目的 70 4.4.2 二維材料堆疊之作法 70 4.4.3 改進後記憶體與電晶體之匹配情形 71 4.5 本章結論與未來展望 74 第5章. 論文總結 75 Reference 76 Appendix 88 | |
dc.language.iso | zh-TW | |
dc.title | 二維材料電阻式記憶體與1T1R結構之研究 | zh_TW |
dc.title | The research of 2D material-based Resistive Random Access Memory and 1T-1R cell | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李敏鴻(Min-Hung Lee),胡璧合(Pi-Ho Hu),陳建宏(Chien-Hung Chen) | |
dc.subject.keyword | 二硫化鉬,電阻式記憶體,1T1R結構,氧電漿轟擊,低功率切換元件,材料改質, | zh_TW |
dc.subject.keyword | Molybdenum disulfide,Memristor,1T1R cell,Oxygen plasma,Low operation power,Material modify, | en |
dc.relation.page | 90 | |
dc.identifier.doi | 10.6342/NTU202004321 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-11-04 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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U0001-0311202018233700.pdf 目前未授權公開取用 | 5.27 MB | Adobe PDF |
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