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標題: | 在單體式三維集體電路上考慮可繞度導向的腳位可使用度最佳化 Routability-Aware Pin Access Optimization for Monolithic Three-Dimensional Designs |
作者: | Run-Yi Wang 王潤一 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 實體設計,腳位可使用度,單體式三維積體電路設計,細部繞線,整數線性規劃, Physical Design,Pin access challenge,Monolithic 3D,Detailed routing,Integer linear program,Dynamic programming, |
出版年 : | 2019 |
學位: | 碩士 |
摘要: | 伴隨著積體電路設計的複雜度越來越高(尤其是製成設計規則數量上的增多),一個合法的細部繞線結果變得越來越難達成。因此,作為一個導致細部繞線困難的主要問題,腳位使用(pin acess challenge)上的難題吸引了研究者們大量的關注。現今,單體式三維積體電路設計(Monolithic three-dimentional)已然成為一向可靠的技術來製造超大型積體電路。這項技術可以利用冗贅的腳位以及空的繞線軌道來緩解腳位使用上的難題。因此,為了有更好的細部可繞線度,需要設計一個專門針對單體式三維積體電路的腳位可用度最佳化的演算法,得以利用這項新技術所提供的優勢。
本篇論文針對在單體式三維積體電路上腳位使用最佳化問題來提高細部繞線的可繞度。我們提出了一個建立在腳位使用幾率上的擁塞程度預估并利用這個預估提出了一個新的加權整數線性規劃方程式。再來,我們提出了一個動態規劃的演算法來改善細部擺置從而得到一個更好的初始解。 實驗結果顯示,我們所提出的方法相較於先前的研究,可以得到更好的腳位可使用度以及細部可繞線度。並且在大型標桿測試基準中得到了驗證。 With the increasing design complexity (especially, the increasing number of design rules), a legal detailed routing solution is becoming more and more difficult to be obtained. As a result, the pin access challenge which is one main issue causing detailed routing problem has attracted substantial attention. Recently, monolithic three-dimensional design (M3D for short) has emerged as a promising technology and become commercially available to accommodate modern VLSI designs. ThisM3D technology can alleviate pin access by providing redundant pins and free rout-ing tracks. This paper addresses the problem of pin access optimization for monolithic 3D designs to improve routability during detailed routing. Unlike existing work that uses integer linear programming to maximize the total number of pre-routed nets on the free routing tracks without considering the influence of a net on pin access congestion, we present a new pin access congestion estimation based on the probability of pin access conflicts and a new weighted ILP formulation. Adynamic programming algorithm is proposed to refine detailed placement to obtain a better initial solution. Experimental results show that our pin access estimation is effective and our algorithm can achieve significant routability improvements. We evaluate our algorithm on the 2015 ISPD Contest benchmarks. Compared with the state-of-the-art flow, our algorithm can outperform 21.14% in DRC errors reduction and 8.09%in the total probability of pin access conflicts with similar runtime. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71447 |
DOI: | 10.6342/NTU201900026 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-108-1.pdf 目前未授權公開取用 | 2.7 MB | Adobe PDF |
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