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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 簡韶逸(Shao-Yi Chien) | |
| dc.contributor.author | Heng Lee | en |
| dc.contributor.author | 李亨 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:00:12Z | - |
| dc.date.available | 2019-02-19 | |
| dc.date.copyright | 2019-02-19 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-02-12 | |
| dc.identifier.citation | S. Han, H. Mao, and W. J. Dally, “Deep compression: Compressing deepneural networks with pruning, trained quantization and huffman coding,”arXiv preprint arXiv:1510.00149, 2015.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71407 | - |
| dc.description.abstract | 深度神經網路在許多邊緣端的電腦視覺任務上已經展現了令人印象深刻的表現，使得在手機上或是物聯網裝置上的深度神經網路加速器需求越來越多。然而，巨量的能量消耗與儲存量的需求使得硬體設計越來越困難。因此，在這篇論文中，我們提出了一個基於壓縮技術(向量量化)來同時減少的神經網路模型的大小與計算量的神經網路加速器。此外，我們設計了一種特化的處理單元與資料流，前者有不同的靜態隨機存取記憶體配置，後者則是可以使加速器支援不同的卷積濾波器的大小，並在輸入或輸出的維度極小時亦保持高度的使用率。與現今最佳的神經網路加速器相比，我們提出的加速器可以減少3.94倍的動態隨機存取記憶體存取量以及在單批次的神經網路推論下減少1.2倍的時間。 | zh_TW |
| dc.description.abstract | Deep neural networks (DNNs) have demonstrated impressive performance in many edge computer vision tasks, causing the increasing demand for DNN accelerator on mobile and internet of things (IoT) devices. However, the massive power consumption and storage requirement make the hardware design challenging. In this paper, we introduce a DNN accelerator based on a model compression technique vector quantization (VQ), which can reduce the network model size and computation cost simultaneously. Moreover, a specialized processing element (PE) is designed with various SRAM bank configurations as well as dataflows such that it can support different codebook/kernel sizes, and keep high utilization under small input or output channel numbers. Compared to the state-of-the-art, the proposed accelerator architecture achieves 3.94 times reduction in memory access and 1.2 times in latency for batch-one inference. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:00:12Z (GMT). No. of bitstreams: 1 ntu-108-R05943046-1.pdf: 1872199 bytes, checksum: 0ed15119be538310f7e76d9b69c8173e (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | Abstract ... i
List of Figures ... v List of Tables ... vii 1 introduction ... 1 1.1 Motivation ... 1 1.2 Challenges ... 1 1.3 Keynote ... 2 1.3.1 Model compression ... 2 1.3.2 Batch size ... 3 1.3.3 Dataflow ... 3 1.4 Contribution ...4 1.5 Thesis Organization ... 4 2 Background Knowledge and Related Work ... 5 2.1 Model Compression Method ... 6 2.1.1 Pruning ... 6 2.1.2 Quantization ... 7 2.2 Neural Network Accelerators ... 8 2.2.1 Convolutional Layer ... 9 2.2.2 Co-design with Algorithm ... 10 2.3 Vector Quantization ... 12 3 Proposed Architecture ... 17 3.1 Overview ... 17 3.2 Processing Element -Baseline ... 19 3.2.1 Precompute Stage ... 20 3.2.2 Dispatch Stage ... 22 3.2.3 Accumulation Stage ... 22 3.2.4 SRAM in PE ... 22 3.3 Processing Element - Improved ... 24 3.3.1 Dispatch Stage ... 24 3.3.2 Precompute Stage ... 24 3.3.3 Accumulation Stage ... 25 3.4 On-Chip SRAM ... 25 3.4.1 Input SRAM ... 25 3.4.2 Output SRAM ... 26 3.5 Dataflow ... 27 3.5.1 Weight Stationary ... 27 3.5.2 Row Stationary-like ... 28 4 Implementation and Experimental Results ... 31 4.1 Implementation ... 31 4.1.1 Processing Element ... 31 4.1.2 Proposed Architecture ... 31 4.2 Experimental result ... 32 5 Conclusions ... 37 Reference ... 39 | |
| dc.language.iso | zh-TW | |
| dc.subject | 神經網路加速器 | zh_TW |
| dc.subject | 模型壓縮 | zh_TW |
| dc.subject | 向量量化 | zh_TW |
| dc.subject | model compression | en |
| dc.subject | neural network accelerator | en |
| dc.subject | vector quantization | en |
| dc.title | 基於向量量化之卷積神經網路處理器架構設計 | zh_TW |
| dc.title | Convolutional Neural Network Accelerator with Vector Quantization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉宗德(Tsung-Te Liu),盧奕璋(Yi-Chang Lu),賴伯承(Bo-Cheng Lai) | |
| dc.subject.keyword | 神經網路加速器,向量量化,模型壓縮, | zh_TW |
| dc.subject.keyword | neural network accelerator,vector quantization,model compression, | en |
| dc.relation.page | 39 | |
| dc.identifier.doi | 10.6342/NTU201900441 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-02-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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