以連續漸進式類比數位轉換器輔助並結合類比雜訊移頻和數位雜訊耦合之50-MHz頻寬連續時間三角積分調變器

Abstract

對於連續時間三角積分調變器來說，迴路濾波器的階數、超取樣率、量化器解析度，三者能夠決定出一個連續時間三角積分器雜訊失真比，但每一種參數的選擇都會有它的好處以及壞處，因此如何能夠在給定的參數選擇下，使得我們的雜訊失真比提升便成了我們的課題。雜訊耦合即是在給定的參數下使得三角積分調變器的雜訊失真比更加提升的一種技術。 此論文呈獻一個使用連續漸進式類比數位轉化器輔助之三階連續時間三角積分調變器，提出結合類比雜訊移頻和數位雜訊耦合之技術，使得連續時間三角積分器能夠在所給定的參數選擇上得到更好的雜訊失真比，並且減少電路的功耗與面積。此技術經模擬驗證，具有一定的功能，足以使迴路穩定且達到高度訊號雜訊比。 本晶片使用台積電四十奈米互補式金屬氧化物半導體1P10M製程所實現，經測試操作於十六億赫茲，在五千萬赫茲的訊號頻寬下，最高可達76.2dB的訊號雜訊失真比。晶片在1.2伏特的電源供應下總共消耗29.6毫瓦。

For a continuous-time ∆Σ modulator, the three factors are important, loop filter orders, oversampling ratio (OSR), quantizer resolution, these three factors can determine a continuous-time delta-sigma modulator signal to noise ratio, but choose these three factors is tricky, so how to improve the CT ∆Σ modulator performance in the given these three factors is a problem. Noise coupling is such technique to improve the signal to noise ratio with given factors. This thesis presents a three-order SAR-assisted continuous-time ∆Σ modulator that incorporates noise shaping and digital noise coupling technique, the combination helps improve the CT ∆Σ modulator performance with the given three factors and reduce power consumption and chip area. Loop stability and noise performance have been observed with functionality by simulation. Fabricated in TSMC 40nm GP 1P10M technology, the proposed CT ∆Σ modulator is tested to operate at 1.6GHz, achieving peak SNDR of 76.2dB over 50MHz signal bandwidth, respectively. The chip dissipates 29.6mW from 1.2V supplies.