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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎 | |
dc.contributor.author | Bo-Yi Li | en |
dc.contributor.author | 李柏毅 | zh_TW |
dc.date.accessioned | 2021-06-17T04:25:00Z | - |
dc.date.available | 2023-08-19 | |
dc.date.copyright | 2018-08-19 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-08-15 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70266 | - |
dc.description.abstract | 隨著積體電路設計尺寸和複雜性的不斷增長,對高質量測試集的需求也隨之出現。 但是,高質量的測試集的大小通常非常大,所以測試圖樣壓縮的方法變得非常重要。
在本論文中,我們提出了一種基於多線程系統的平行化自動圖樣產生技術。 所提出的ATPG可以提高壓縮效率以減少測試圖樣數目。而確定性也在本論文中被考慮。 本論文提出的方法在ISCAS89和ITC99測試電路上進行實驗,實驗結果顯示,所提出的技術在減少測試圖樣數目方面有2.7%~41%的改進,而不會犧牲故障覆蓋率及時間。 | zh_TW |
dc.description.abstract | As VLSI designs continue to grow in size and complexity, the demand for high-quality test sets arises for testing. However, the size of the high-quality test set is usually very large so the method of test pattern compaction becomes very important.
In this thesis, we proposed a parallel N-pattern compaction ATPG which is based on a multi-threading system. The proposed ATPG can improve the compaction efficiency to reduce the test pattern count. Determinism is also considered in our technique. The proposed techniques are validated using ISCAS89 (International Symposium on Circuits and Systems) and ITC99 benchmark circuits. The experimental results show that the proposed techniques have considerable improvement considerable improvement from 2.7% to 41% in reducing test pattern count without sacrificing fault coverage and run time. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T04:25:00Z (GMT). No. of bitstreams: 1 ntu-107-R05943087-1.pdf: 1382013 bytes, checksum: 29abfc4be57788640727a8d5b1b4ef05 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Previous works and Preliminaries 3 2.1 Typical Serial ATPG 3 2.2 Test Compaction Technique 4 2.2.1 Dynamic Compaction 4 2.2.2 Static Compaction 5 2.2.3 Other Compaction Techniques 6 2.3 Parallel ATPG Techniques 6 2.3.1 Fault Partitioning 7 2.3.2 Search Space Partitioning 8 2.3.3 Heuristic Parallelization 9 2.3.4 Circuit Partitioning 10 2.4 Determinism Techniques 10 Chapter 3 Proposed Techniques 12 3.1 Overall Strategy Flow 12 3.2 Parallel ATPG with Master-and-Slave Structure 13 3.2.1 Implementation 13 3.2.2 Master Procedure 14 3.2.3 About Determinism 15 3.2.4 Merge Process 17 3.2.5 Slave Procedure 19 3.2.6 The Advantage Compared to Typical Dynamic Compaction 20 3.2.7 Backtrack Limit Issue 21 3.3 Comparison with the Proposed ATPG 23 3.3.1 Implementation 23 3.3.2 Procedure in Each Thread 23 3.3.3 About Determinism 24 3.3.4 Merge Process 25 3.3.5 The Disadvantage of the Method 26 Chapter 4 Experiment Result 27 4.1 Backtrack Limit Issue 27 4.2 Previous Works Setup 28 4.3 Comparison Between 3 Merge Methods 29 4.4 The Result of the Parallel ATPG with Master-and-Slave Structure 30 4.5 The Result of the Comparison Parallel ATPG 32 4.6 Comparison between Two Proposed Parallel ATPG 34 4.7 Pattern Count Result with Same Fault Coverage 35 4.8 About Determinism 36 Chapter 5 Conclusion 37 REFERENCE 38 | |
dc.language.iso | en | |
dc.title | 可降低測試圖樣數目之平行化自動測試圖樣產生技術 | zh_TW |
dc.title | Reducing Test Pattern Count by A Parallel N-pattern
Compaction ATPG | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂學坤,李進福,黃炫倫 | |
dc.subject.keyword | 積體電路測試,自動測試圖樣產生技術,測試圖樣壓縮,平行化,測試膨脹,確定性,多線程, | zh_TW |
dc.subject.keyword | VLSI testing,ATPG,test pattern compaction,parallel,test inflation,determinism,multi-threading, | en |
dc.relation.page | 41 | |
dc.identifier.doi | 10.6342/NTU201803400 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-08-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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