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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Chia-Te Lin | en |
| dc.contributor.author | 林家德 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:18:13Z | - |
| dc.date.available | 2028-06-28 | |
| dc.date.copyright | 2018-07-03 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-06-29 | |
| dc.identifier.citation | [1] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, 'An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications,' in IEEE Journal of Solid-State Circuits.
[2] R. Giterman, A. Fish, A. Burg and A. Teman, 'A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 4, pp. 1245-1256, April 2018. [3] E. Yoshida and T. Tanaka, 'A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,' in IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 692-697, April 2006. [4] N. Rodriguez, S. Cristoloveanu and F. Gamiz, 'Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates,' in IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2371-2377, Aug. 2011. [5] Y. D. Tan and J. G. Hwu, “2-State Current Characteristics of MOSCAP with Ultrathin Oxide and Metal Gate,” ECS Solid State Lett., vol. 4, no. 12, pp. N23-N25, Nov. 2015. [6] K. H. Tseng, C. S. Liao and J. G. Hwu, 'Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness,' in IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 1011-1015, Nov. 2017. [7] N. Yang, W. K. Henson, J. R. Hauser and J. J. Wortman, 'Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices,' in IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464-1471, Jul 1999. [8] Wen-Chin Lee and Chenming Hu, 'Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,' in IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1366-1373, Jul 2001. [9] C. W. Lee, “A comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., 2013. [10] R. Tsu and L. Esaki, “Tunneling in A Finite Superlattice,” Appl. Phys. Lett., vol. 22, no. 11, pp. 562, Mar. 1973. [11] Y. P. Lin, and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” J. Electrochem. Soc., vol. 151, no. 12, pp. G853-G857, Oct. 2004. [12] C. S. Liao and J. G. Hwu, 'Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor,' in IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 2061-2065, June 2015. [13] E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York: Wiley, pp. 74, 1981. [14] K. J. Yang and Chenming Hu, 'MOS capacitance measurements for high-leakage thin dielectrics,' in IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1500-1501, Jul 1999. [15] Berkeley Device Group: www-device.eecs.berkeley.edu/qmcv/. [16] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, pp. 230-236, 1957. [17] Gong, D., Grimes, C., Varghese, O., Hu, W., Singh, R., Chen, Z., & Dickey, E. (2001). Titanium oxide nanotube arrays prepared by anodic oxidation. Journal of Materials Research, 16(12), 3331-3334. [18] Chieh-Chih Ting, Yen-Hao Shih and Jenn-Gwo Hwu, 'Ultralow leakage characteristics of ultrathin gate oxides (~3 nm) prepared by anodization followed by high-temperature annealing,' in IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 179-181, Jan 2002. [19] M. J. Jeng, “Application of Anodic Oxidation and Rapid Thermal Treatment on Thin Gate Oxides and Radiation-Hard CMOS Circuit Design” Ph. D. dissertation, Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R. O. C., 1996. [20] S.K. Ghandhi, VLSI Fabrication Principles, 2nd ed., Wiley-Interscience, pp. 487-495, 1994. [21] M. A. Siddiqi, “DRAM cell development,” in Dynamic RAM: Technology Advancements. Boca Raton, FL, USA: CRC Press, 2013. [22] Y. Aoki et al., “Ultra-high-performance 0.13-μm embedded DRAM technology using TiN/HfO2/TiN/W capacitor and body-slightly-tied SOI” in IEDM Tech. Digest, 2002, pp. 831-834. [23] F. Hamzaoglu et al., 'A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology,' in IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 150-157, Jan. 2015. [24] N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara and C. Anghel, 'Tunnel FET based refresh-free-DRAM,' Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 914-917. [25] N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara and C. Anghel, 'Tunnel FET based ultra-low-leakage compact 2T1C SRAM,' 2017 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2017, pp. 71-75. [26] K. C. Chun, P. Jain, T. H. Kim and C. H. Kim, 'A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches,' in IEEE Journal of Solid-State Circuits, vol. 47, no. 2, pp. 547-559, Feb. 2012. [27] Dinesh Somasekhar, Yibin DaleYe, Paolo Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi,“2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 174–185, 2009. [28] Y. S. Park, D. Blaauw, D. Sylvester and Z. Zhang, 'Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM,' in IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 783-794, March 2014. [29] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, 'An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications,' ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, 2017, pp. 308-311. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69525 | - |
| dc.description.abstract | 本篇論文中，我們藉由調整傳統金氧半穿隧二極體的結構使元件的暫態反應及雙態現象獲得提升。在論文的第二章中我們透過製備邊緣延伸性閘極薄金屬的金氧半穿隧二極體結構讓邊緣的延伸性薄金屬在偏壓下呈現電阻特性，使得載子在來回掃動的電容-電壓量測中的暫態反應增加而展現明顯的雙態電容特性和電容遲滯現象。而為了測試這個元件的電容雙態特性是否夠穩定來作為傳統隨機存取記憶體之應用，我們對此元件進行了基本的耐久性測試，並且對於此元件在脈衝操作下的反應機制進行了更深入的研究。在論文的第三章中，透過調變傳統金氧半穿隧二極體在邊緣絕緣層的氧化層厚度來產生結構的不均勻性。由於氧化層厚度的差異，使得元件在電流-電壓量測中會產生額外的暫態電流而造成來回掃動的電流差異，並顯現出明顯的雙態電流特性。此外，我們也發現此元件的雙態特性會與量測的速率和掃動的範圍有關。 | zh_TW |
| dc.description.abstract | In this thesis, transient response and two-state characteristics of our targeting devices have definitely gotten enhanced through some simple adjustment to the well-investigated conventional MIS structure. In chapter 2, by thinning the edging part of gate metal for traditional MIS to reveal the resistance-like property, carriers’ transient response has been enlarged through forward and reverse C-V measurements, displaying distinguishable two-state capacitance and increasing C-V hysteresis through voltage sweeping. Furthermore, endurance characteristic is also demonstrated to test the capability of being a future alternative of memory applications. Also, detailed mechanism under bias condition is then discussed on both structures. In chapter 3, in another way, we fabricate MIS devices with uneven oxide (UEOMIS) at the edge to create structural non-uniformity. Through the variation of current conduction between bulk and edge, transient phenomenon is then discovered during I-V measurements, exhibiting obvious two-state characteristic of current. Moreover, further investigation has been practiced to show that the transient phenomenon in UEOMIS devices is closely related to the sweeping rate and sweeping range. Last but not least, endurance and retention characteristics are also applied to check out the reliability of our devices. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:18:13Z (GMT). No. of bitstreams: 1 ntu-107-R05943053-1.pdf: 5462588 bytes, checksum: 1ba92432e49ed871e4c8ae90d76eeb0d (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | Content
摘要……………………………………………………………………… I Abstract………………………………………………………………… II Content………………………………………………………………… III Table Caption………………………………………………………… VI Figure Caption ……………………………………………………… VII Chapter 1 Introduction………………………………………………… 1 1-1 Motivation…………………………………………………………………… 1 1-2 Electrical Characteristics of MIS (p) tunnel diode………………………… 3 1-3 Determination of Oxide Thickness by Quantum Mechanical Fitting……… 5 1-4 Anodic Oxidation System….……………………………………………… 7 Chapter 2 Enhanced Transient Response and Characteristics in MIS (p) Structure with Elongated Thin Metal Gate…………12 2-1 Introduction………………………………………………………………… 13 2-1-1 Overview………………………………………………………………13 2-1-2 Two-State Current Behavior………………………………………… 14 2-2 Experimental……………………………………………………………… 15 2-3 Results and Discussion……………………………………………………… 16 2-3-1 Two-State Characteristics of Capacitance-Voltage Profiling………… 16 2-3-2 Endurance Characteristics…………………………………………… 17 2-3-3 Operation Consideration……………………………………………… 19 2-3-4 Mechanism Study of Write/Read…………………………………… 20 2-3-5 Observation of Voltage Shifts at Constant Capacitance……………… 22 2-4 Summary………………………………………………………………………… 24 Chapter 3 Amplification of Transient Behavior in MIS (p) Structure by Fringing Oxide Thickness Modulation……………… 36 3-1 Introduction…………………………………………………………………… 36 3-2 Experimental…………………………………………………………………… 37 3-3 Results and Discussion……………………………………………… 39 3-3-1 I-V and C-V Characteristics…………………………………………… 39 3-3-2 Inspection of Two-State Behavior………………………………… 40 3-3-2 Endurance and Retention……………………………………………… 42 3-4 Summary…………………………………………………………………… 43 Chapter 4 Conclusion and Future Work…………………………… 51 4-1 Conclusion……………………………………………………………………… 51 4-2 Memory Applications and Benchmark…………………………………… 52 4-3 Future Work………………………………………………………………… 53 Reference……………………………………………………………… 56 | |
| dc.language.iso | en | |
| dc.subject | MIS Tunnel diode | zh_TW |
| dc.subject | memory | zh_TW |
| dc.subject | two-state characteristics | zh_TW |
| dc.subject | structural non-uniformity | zh_TW |
| dc.subject | 不均勻結構 | en |
| dc.subject | 金氧半穿隧二極體 | en |
| dc.subject | 記憶體 | en |
| dc.subject | 雙態特性 | en |
| dc.title | 不均勻結構金氧半穿隧二極體之雙態特性與暫態行為 | zh_TW |
| dc.title | Two-State Characteristics and Transient Behavior in Metal-Insulator-Semiconductor Tunnel Diode with Structural Non-Uniformity | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林致廷(Chih-Ting Lin),吳幼麟(You-Lin Wu) | |
| dc.subject.keyword | MIS Tunnel diode,memory,two-state characteristics,structural non-uniformity, | zh_TW |
| dc.subject.keyword | 金氧半穿隧二極體,記憶體,雙態特性,不均勻結構, | en |
| dc.relation.page | 59 | |
| dc.identifier.doi | 10.6342/NTU201801189 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-06-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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