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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂學士 | |
dc.contributor.author | Pen-Li Huang | en |
dc.contributor.author | 黃本立 | zh_TW |
dc.date.accessioned | 2021-05-17T09:21:57Z | - |
dc.date.available | 2017-03-19 | |
dc.date.available | 2021-05-17T09:21:57Z | - |
dc.date.copyright | 2012-03-19 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-02-06 | |
dc.identifier.citation | Bibliography of Chapter 1
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/6946 | - |
dc.description.abstract | 將以電感耦合型電漿蝕刻為主,利用微機電矽基板蝕刻技術(深槽技術),應用於CMOS微波被動元件,特別是高頻微波濾波器,以檢驗其相容性與功效。實驗結果顯示,藉由深槽技術將CMOS元件底下具有損耗性的矽移除之後,該濾波器insert loss相較於未施作深槽技術之濾波器為佳。
除了上述被動元件外,基於考慮先進CMOS製程過於昂貴,藉由摺疊設計四分之一波長之被動濾波器來減少濾波器的面積,並設計工作頻率在V頻段之濾波器,並可藉由分別改變金屬-絕緣層-金屬電容的重疊長度調整該電容值,控制低頻傳輸零點,以及改變L-C共振腔與濾波器地端的間隔調整高頻傳輸零點,形成V頻段帶通濾波器,再以深槽技術將CMOS元件底下具有損耗性的矽移除,使得該濾波器的輸入損耗的3dB帶頻頻寬範圍為46.5~85.5 GHz,最小輸入損耗在60GHz頻率有-1.8dB。就現有所知道的V頻段帶通濾波器特性最佳。 此外,本研究提出遞藥系統整合在晶片上,藉由電極通電後將水電解產生微氣泡,藉由所產生的力開啟藥箱釋放藥物。經代工廠將無線技術中電路元件製作整合在晶片上,再將該技術施作應用於生醫送藥系統,利用CMOS製程將在定義藥箱後,藉由深槽技術移除矽基板後,再以顯式蝕刻將保護層及二氧化矽移除,即完成藥箱結構,再充填藥物結構,完成晶片面積2.48㎟,消耗功率約7.57毫瓦,並驗證體外實驗可行性。 最後,本研究將矽基板損耗在微波濾波器所造成的影響,作為提供為未來相關電子元件矽基板損耗之研究參考。 | zh_TW |
dc.description.provenance | Made available in DSpace on 2021-05-17T09:21:57Z (GMT). No. of bitstreams: 1 ntu-101-D91943018-1.pdf: 3581238 bytes, checksum: c2bf6ff3516829d4a4dab65c8776ee5c (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | Table of Contents
1.Introduction 1 Bibliography of Chapter 1 6 2.Deep Trench Technology 7 2.1 Earlier Methods used to Improve Inductive Devices 7 2.2 Inductively-coupled Plasma Etching 20 2.3 Deep Trench Technology 27 Bibliography of Chapter 2 30 3.Microwave Passive Filters 31 3.1 Introduction 31 3.1.1 Deep Trench Technology 32 3.1.2 Transmission lines 33 3.2 E-band Bandpass Coplanar Filters 39 3.2.1 Filter Structure 39 3.2.2 Measurement Results and Discussions 42 3.3 50 GHz/60 GHz Phi Filters 46 3.3.1 Filter Design and Structure 47 3.3.2 Measurement Results and Discussions 49 3.4 V-band CMOS bandpass filter 55 3.4.1 Filter Structure 55 3.4.2 Measurement Results and Discussions 56 3.5 CPW Band-Pass Filter Utilizing the LC Structure 59 3.5.1 Filter Structure 59 3.5.2 Measurement Results and Discussions 63 3.6 SiGe HBT Ultrawideband Low-Noise Amplifier 72 3.6.1 UWB LNA Design 73 3.6.2 Measurement Results and Discussions 74 3.7 Summary 79 Bibliography of Chapter 3 83 4.A Controlled-release Drug Delivery System on a Chip Using Electrolysis 89 4.1 Introduction 89 4.2 System Architecture 92 4.3 On-Chip Electrolysis 94 4.4 Drug Reservoir Design and Fabrication 95 4.5 Sub-Blocks 99 4.6 Experiment Results 99 4.7 Practical Issues 104 Bibliography of Chapter 4 106 5.Conclusions 111 List of Figures Fig. 2.1: Current distribution in a metal strip: skin effect and proximity effect 8 Fig. 2.2: Section of a planar inductor and mapping lumped model 9 Fig. 2.3: Model descriptions 12 Fig. 2.4: Problems with solid ground shield 14 Fig. 2.5: Electric field and magnetic field penetration 16 Fig. 2.6: Patterned ground shield of a planar inductor 16 Fig. 2.7: Prior methods to improve inductors (a) thickening dielectric (b)front-side etching (c) proton-implementation/porous silicon 18 Fig. 2.8: Conventional plasma etching system 22 Fig. 2.9: Illustration of alternating passivating and etch cycles 23 Fig. 2.10: Inductively-coupled plasma etching system 25 Fig. 2.11: Schematic diagram of STS inductively coupled etch system used for ASETM 27 Fig. 2.12: Procedure of Deep Trench Technology 28 Fig. 2.13: Result of substrate removal 29 Fig. 3.1: Processing steps of the backside ICP deep-trench etching technology 33 Fig. 3.2: Complete small-signal equivalent circuit model of a TL inductor, in which the effect of test pads is included 36 Fig. 3.3: Measured S21 versus frequency characteristics of STD TL-IND1, ICP TL-IND1, ICP TL- IND2, and ICP TL-IND3 and an equivalent circuit does to calculate the S21 of TL inductors 37 Fig. 3.4: (a) Front-side die photo (before ICP etching) of filter-1. (b) top-view and 3D schematic diagrams of filter-1. (c) backside die photo (after ICP etching) of filter-2 41 Fig. 3.5: Measure and simulated (a) S11 and (b) S21 of filter-1 after the backside ICP etching 43 Fig. 3.6: Measured (a) S11 and (b) S21 of filter-1 both before and after the backside ICP etching 44 Fig. 3.7 Measured (a) S11 and (b) S21 of filter-2 both before and after the backside ICP etching 44 Fig. 3.8: The lumped-element model of the filter 45 Fig. 3.9: Layout of the proposed band-pass filter (a) the 50GHz filter and (b) 3D schematic diagram at the input port of the proposed band-pass filter 48 Fig. 3.10: Backside chip photo 49 Fig. 3.11: S11 and S21 of the 50GHz filter 49 Fig. 3.12: S11 and S21 of the 60GHz filter 51 Fig. 3.13: Maximum available power gain derived from the measured S parameters 51 Fig. 3.14: The lumped-element model of the filter 52 Fig. 3.15: Comparison between modeling and measurement results 54 Fig. 3.16: Equivalent circuit (a), front-side die photo (b), and backside die photo (after ICP etching) of fabricated V-band CMOS filter (c) 57 Fig. 3.17: Simulated and measured S21 and S11 against frequency characteristics of proposed filter 58 Fig. 3.18: (a) Top view and cross-sectional schematic diagrams, and (b) small-signal equivalent circuit model of the V-band CMOS band-pass filter 60 Fig. 3.19: (a) Simulated S21 and S11 versus frequency characteristics of the band-pass filter at various MIM capacitor dimensions. (b) Simulated S21 and S11 versus frequency characteristics of the band-pass filter at various LC resonator gaps 62 Fig. 3.20: (a) Front-side die photo, and (b) backside die photo (after ICP etching) of the fabricated V-band CMOS filter 63 Fig. 3.21: Measured and simulated S21 and S11 versus frequency characteristics of the band-pass filter both with and without the silicon substrate removal 65 Fig. 3.22: The lumped-element model of the filter 66 Fig. 3.23: (a) Chip micrograph, and (b) measured S-parameters of a test filter with the series capacitor (Cs) but without the LC resonator 68 Fig. 3.24: (a) Chip micrograph, and (b) measured S-parameters of a test filter without the series capacitor (Cs) but with the LC resonator 69 Fig. 3.25: (a) Schematic of the SiGe HBT UWB LNA. (b) Front side (before the etching) and backside(after the etching) chip micrographs of the SiGe HBT UWB LNA. The LNA occupied an area of 0.6×0.4 mm2, excluding the test pads 76 Fig. 3.26: (a) shows the measured input return loss (S11) versus frequency characteristics of the SiGe HBT UWB LNA both before and after the backside ICP etching 77 Fig. 3.27:The lumped-element circuit extracted from the first-order bandpass filter 79 Fig. 4.1: Architecture of SOC for drug delivery 93 Fig. 4.2: Proposed drug delivery system in package 96 Fig. 4.3: Opening of the integrated reservoir: (a) microbubbles generated on the surface of electrodes by electrolysis, (b) membrane ruptured by gas pressure 96 Fig. 4.4: Post-IC processing steps 98 Fig. 4.5: Die photos:(a) front-side (b) back-side 98 Fig. 4.6: Drug delivery SOC 100 Fig. 4.7: Measured sensitivity of the OOK receiver 102 Fig. 4.8: In-Vitro measurement setup 103 Fig. 4.9: Measured drug release results: (a) before electrolysis (b) after electrolysis 101 Fig. 4.10: In vitro measurement results of the concentration of the fluorescent dye versus time after an opening command is given 103 List of Tables Table 2.1: Etching parameters 27 Table 3.1: Extracted small-signal equivalent circuit parameters of the E-band bandpass filter both before and after the ICP etching 46 Table 3.2: Extracted small-signal equivalent circuit parameters of the 50 GHz filter both before and after the ICP etching 53 Table 3.3: Extracted small-signal equivalent circuit parameters of the V-band bandpass filter both before and after the ICP etching 67 Table 3.4: Summary of the implemented V-band CMOS bandpass filter,and recently reported state-of-the-art CMOS bandpass filters 71 Table 4.1: Power and energy in different activation techniques 104 | |
dc.language.iso | en | |
dc.title | 應用電感耦合型電漿蝕刻且與CMOS製程相容之微機電微波濾波器及生醫遞送藥箱 | zh_TW |
dc.title | Micromachined Microwave Filter and Biomedical Drug Delivery Box Using CMOS-Compatible ICP Deep Trench Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-1 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 孫台平,林佑昇,楊燿州,邱弘緯,汪濤 | |
dc.subject.keyword | 電感耦合型電漿蝕刻,互補型金氧半,微機電,深槽技術,遞藥,系統整合晶片,體外實驗, | zh_TW |
dc.subject.keyword | ICP,CMOS,MEMS,Deep Trench Technology,drug delivery,system on a chip (SOC),In-Vitro, | en |
dc.relation.page | 113 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2012-02-07 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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